Semiconductor Device Having Overload Current Carrying Capability

Patent metadata

Field	Value
Publication number	US-2016204097-A1
Application number	US-201514971677-A
Country	US
Kind code	A1
Filing date	Dec 16, 2015
Priority date	Dec 17, 2014
Publication date	Jul 14, 2016
Grant date	—

Abstract

A semiconductor device includes a semiconductor region having charge carriers of a first conductivity type, a transistor cell in the semiconductor region, and a semiconductor channel region in the transistor cell and having a first doping concentration of charge carriers of a second conductivity type. A semiconductor auxiliary region in the semiconductor region has a second doping concentration of charge carriers of the second conductivity type, which is at least 30% higher than the first doping concentration. A pn-junction between the semiconductor auxiliary region and the semiconductor region is positioned as deep or deeper in the semiconductor region as a pn-junction between the semiconductor channel region and the semiconductor region. The semiconductor auxiliary region is positioned closer to the semiconductor channel region than any other semiconductor region having charge carriers of the second conductivity type and that forms a further pn-junction with the semiconductor region.

First claim

What is claimed is:

1 . A semiconductor device, comprising:
a semiconductor region, the semiconductor region comprising charge carriers of a first conductivity type; a transistor cell included in the semiconductor region; a semiconductor channel region included in the transistor cell, the semiconductor channel region comprising a first doping concentration of charge carriers of a second conductivity type complementary to the first conductivity type, wherein a transition between the semiconductor channel region and the semiconductor region forms a first pn-junction; a semiconductor auxiliary region included in the semiconductor region and different from the semiconductor channel region, the semiconductor auxiliary region comprising a second doping concentration of charge carriers of the second conductivity type, the second doping concentration being at least 30% higher as compared to the first doping concentration, wherein a transition between the semiconductor auxiliary region and the semiconductor region forms a second pn-junction, the second pn-junction being positioned as deep or deeper in the semiconductor region as compared to the first pn-junction, and wherein the semiconductor auxiliary region is positioned closest to the semiconductor channel region as compared to any other semiconductor region of the semiconductor device that comprises charge carriers of the second conductivity type and that forms a further pn-junction with the semiconductor region; and a diode cell included in the semiconductor region, the diode cell comprising a semiconductor anode region, wherein the semiconductor anode region comprises a third doping concentration of charge carriers of the second conductivity type, and wherein the second doping concentration is higher than the third doping concentration.

2 . The semiconductor device of claim 1 , further comprising a semiconductor source region included in the transistor cell and being in contact with the semiconductor channel region, the semiconductor source region comprising charge carriers of the first conductivity type.

3 . The semiconductor device of claim 1 , wherein a transition between the semiconductor anode region and the semiconductor region forms a third pn-junction, and wherein the second pn-junction is positioned as deep or deeper in the semiconductor region as compared to the third pn-junction.

4 . The semiconductor device of claim 1 , further comprising at least two first trenches included in the diode cell, each first trench comprising a first electrode and a first dielectric, each first dielectric insulating the first electrode of the respective first trench from the semiconductor body, wherein semiconductor anode region is positioned between two of the first trenches and in contact with the first dielectrics of the two first trenches.

5 . The semiconductor device of claim 1 , further comprising an auxiliary cell included in the semiconductor region, the auxiliary cell comprising the semiconductor auxiliary region and being positioned adjacent to the transistor cell.

6 . The semiconductor device of claim 5 , wherein a distance between the auxiliary cell and the transistor cell is lower compared to a distance between the diode cell and the transistor cell.

7 . The semiconductor device of claim 1 , further comprising at least two second trenches included in the transistor cell, each second trench comprising a gate electrode and a second dielectric, each second dielectric insulating the gate electrode of the respective second trench from the semiconductor region, wherein:
the semiconductor auxiliary region is in contact with the semiconductor channel region and positioned between two of the second trenches; or at least one of the second trenches is positioned between the semiconductor auxiliary region and the semiconductor channel region, both the semiconductor auxiliary region and the semiconductor channel region being in contact with the second dielectric of the at least one second trench; or the semiconductor auxiliary region is positioned as deep or deeper in the semiconductor region as compared to the second trenches and apart from the semiconductor channel region.

8 . The semiconductor device of claim 1 , wherein the second doping concentration of the semiconductor auxiliary region is at least twice as high as the first doping concentration of the semiconductor channel region.

9 . The semiconductor device of claim 1 , wherein the semiconductor device is operable in at least one of a forward current mode and a reverse current mode, wherein the semiconductor channel region is configured to conduct at least a part of a nominal load current in a forward direction if the semiconductor device is operated in the forward current mode, and wherein the semiconductor auxiliary region is configured to conduct at least a part of an overload current in a reverse direction if the semiconductor device is operated in the reverse current mode.

10 . The semiconductor device of claim 1 , wherein the second pn-junction is positioned at a depth at least 50 nm deeper as compared to the depth of the first pn-junction.

11 . A semiconductor device operable in at least one of a forward current mode and a reverse current mode and being configured to conduct a load current in a forward direction during the forward current mode and to conduct a load current in a reverse direction during the reverse current mode, the semiconductor device comprising:
a semiconductor region; and a controllable charge carrier injector configured to inject charge carriers into the semiconductor region and being responsive to a control signal, wherein the controllable charge carrier injector is further configured to set the semiconductor device, when being in the reverse current mode, either into a nominal state or into an overload state in dependence of the control signal, wherein in the nominal state, the controllable charge carrier injector is configured to induce a first charge carrier density within the semiconductor region so as to allow the semiconductor region to conduct a nominal load current in the reverse direction, wherein in the overload state, the controllable charge carrier injector is configured to induce a second charge carrier density within the semiconductor region so as to allow the semiconductor region to conduct an overload current in the reverse direction, the second charge carrier density being higher than the first charge carrier density.

12 . The semiconductor device of claim 11 , further comprising a gate electrode for operating the semiconductor device, the gate electrode being electrically coupled to the controllable charge carrier injector and configured to receive a gate signal and to generate the control signal based on the received gate signal.

13 . The semiconductor device of claim 12 , wherein, in the forward current mode, the gate electrode is configured to turn-off the semiconductor device based on the received gate signal so as to block flow of a load current in the forward direction.

14 . The semiconductor device of claim 11 , wherein the second charge carrier density is at least twice as high as the first charge carrier density.

15 . The semiconductor device of claim 11 , wherein the semiconductor region comprises charge carriers of a first conductivity type and wherein a transistor cell is included in the semiconductor region that comprises a semiconductor channel region, the semiconductor channel region comprising a first doping concentration of charge carriers of a second conductivity type complementary to the first conductivity type, wherein a trans

Assignees

• Infineon Technologies Ag

Inventors

• Laven Johannes Georg
• Baburske Roman
• Basler Thomas
• Brandt Philip Christoph
• Cotorogea Maria

Classifications

• H03K17/0828

  in composite switches · CPC title

• H10D62/106 Primary

  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions · CPC title

• H10D62/128

  Anode regions of diodes · CPC title

• H10D89/713

  including a PNP transistor and a NPN transistor, wherein each of said transistors has its base region coupled to the collector region of the other transistor, e.g. silicon controlled rectifier [SCR] devices · CPC title

• H10D89/611

  using diodes as protective elements · CPC title