Detection of an incorrectly located read voltage

Patent metadata

Field	Value
Publication number	US-12009040-B2
Application number	US-202217939756-A
Country	US
Kind code	B2
Filing date	Sep 7, 2022
Priority date	May 7, 2020
Publication date	Jun 11, 2024
Grant date	Jun 11, 2024

Abstract

A memory device to program a group of memory cells to store multiple bits per memory cell. Each bit per memory cell in the group from a page. After determining a plurality of read voltages of the group of memory cells, the memory device can read the multiple pages of the group using the plurality of read voltages. For each respective page in the multiple pages, the memory device can determine a count of first memory cells in the respective page that have threshold voltages higher than a highest read voltage, among the plurality of read voltages, used to read the respective page. The count of the first memory cells can be compared with a predetermined range of a fraction of memory cells in the respective page to evaluate the plurality of read voltages (e.g., whether any of the read voltages is in a wrong voltage range).

First claim

What is claimed is:

1. A device, comprising:
a plurality of memory cells; and
a circuit configured to, in response to a read command:
apply a voltage to read the memory cells;
determine, among the plurality of memory cells, a count of first memory cells having threshold voltages higher than the voltage; and
calibrate reading of the memory cells based at least in part on the count.

2. The device of claim 1 , wherein the circuit is further configured to program a threshold voltage of each respective memory cell, among the plurality of memory cells, to one of a plurality of voltage regions to represent more than one bit of data.

3. The device of claim 2 , wherein the circuit is further configured to identify a plurality of voltages to read the plurality of memory cells; and wherein the voltage is a highest one among the plurality of voltages.

4. The device of claim 3 , wherein the circuit is further configured to compare the count with thresholds representative of a predetermined range of a fraction of a count of the memory cells.

5. The device of claim 4 , further comprising:
an integrated circuit die containing the memory cells; and
an integrated circuit package configured to enclose the integrated circuit die.

6. The device of claim 1 , wherein the circuit is further configured to:
read the plurality of memory cells at a plurality of test voltages in a test voltage range centered at a respective voltage among a plurality of voltages;
determine, among the plurality of memory cells applied a respective test voltage among the plurality of test voltages, a count of second memory cells having a predetermined state; and
calibrate the respective voltage based on the count of the second memory cells.

7. The device of claim 6 , wherein the plurality of test voltages are evenly distributed in the test voltage range.

8. The device of claim 6 , wherein the circuit is configured to determine, based on the count of the first memory cells, whether to calibrate the respective voltage through reading the plurality of memory cells at the plurality of test voltages.

9. A method, comprising:
applying a voltage to read a plurality of memory cells in a device;
determining, among the plurality of memory cells, a count of first memory cells having threshold voltages higher than the voltage; and
determining, based on the count of the first memory cells, whether the voltage is erroneous for reading the memory cells.

10. The method of claim 9 , further comprising:
programming a threshold voltage of each respective memory cell, among the plurality of memory cells, to one of a plurality of voltage regions to represent more than one bit of data.

11. The method of claim 10 , further comprising:
identifying a plurality of voltages to read the plurality of memory cells;
wherein the voltage is a highest one among the plurality of voltages.

12. The method of claim 11 , further comprising:
comparing the count with thresholds representative of a predetermined range of a fraction of a count of the memory cells.

13. The method of claim 12 , further comprising:
reading the plurality of memory cells at a plurality of test voltages in a test voltage range centered at a respective voltage among the plurality of voltages;
determining, among the plurality of memory cells applied a respective test voltage among the plurality of test voltages, a count of second memory cells having a predetermined state; and
calibrating the respective voltage based on the count of the second memory cells.

14. The method of claim 13 , wherein the plurality of test voltages are evenly distributed in the test voltage range.

15. The method of claim 13 , further comprising:
determining, based on the count of the first memory cells, whether the respective voltage is erroneous for calibration through reading the plurality of memory cells at the plurality of test voltages.

16. A system, comprising:
a processing device configured to provide a command; and
a memory device having a plurality of memory cells and configured to:
apply, in response to the command, a voltage to read the memory cells;
determine, among the plurality of memory cells, a count of first memory cells having threshold voltages higher than the voltage; and
determine, based on the count of the first memory cells, whether the voltage is erroneous for reading the memory cells.

17. The system of claim 16 , wherein the memory device is further configured to identify a plurality of voltages to read the plurality of memory cells; and the voltage is a highest one among the plurality of voltages.

18. The system of claim 17 , wherein the memory device is further configured to determine that the voltage is erroneous when the count is outside of thresholds representative of a predetermined range of a fraction of a count of the memory cells.

19. The system of claim 18 , wherein the memory device is further configured to:
read the plurality of memory cells at a plurality of test voltages in a test voltage range centered at a respective voltage among the plurality of voltages;
determine, among the plurality of memory cells applied a respective test voltage among the plurality of test voltages, a count of second memory cells having a predetermined state; and
calibrate the respective voltage based on the count of the second memory cells.

20. The system of claim 17 , wherein the memory device is further configured to determine, based on the count of the first memory cells, whether the respective voltage is outside of a range for calibration through reading the plurality of memory cells at the plurality of test voltages.

Assignees

• Micron Technology Inc

Inventors

• Parthasarathy Sivagnanam
• Fitzpatrick James
• Khayat Patrick Robert
• Alhussien Abdelhakim S

Classifications

• G11C29/46

  Test trigger logic · CPC title

• G11C16/26 Primary

  Sensing or reading circuits; Data output circuits · CPC title

• G11C2207/2254

  Calibration · CPC title

• G11C29/44

  Indication or identification of errors, e.g. for repair · CPC title

• G11C29/12005 Primary

  comprising voltage or current generators · CPC title