Read voltage tracking method, memory storage device and memory control circuit unit

Patent metadata

Field	Value
Publication number	US-9892799-B1
Application number	US-201715472293-A
Country	US
Kind code	B1
Filing date	Mar 29, 2017
Priority date	Feb 8, 2017
Publication date	Feb 13, 2018
Grant date	Feb 13, 2018

Abstract

A read voltage tracking method, a memory storage device and a memory control circuit unit are provided. The method includes obtaining a plurality of test read voltages corresponding to a plurality of voltage adjustment values, and obtaining an optimal read voltage according to the voltage adjustment values. The step of obtaining the test read voltages includes obtaining a second test read voltage by adjusting a first test read voltage according to a first voltage adjustment value, and obtaining a third test read voltage by adjusting the second test read voltage according to a second voltage adjustment value, and the first test read voltage is a preset test read voltage, the first voltage adjustment value is a preset voltage adjustment value, and the first voltage adjustment value is different from the second voltage adjustment value.

First claim

What is claimed is:

1. A read voltage tracking method for a rewritable non-volatile memory module comprising a plurality of memory cells, the read voltage tracking method comprising:
obtaining a plurality of test read voltages, wherein the test read voltages correspond to a plurality of voltage adjustment values; and
obtaining an optimal read voltage from the test read voltages according to the voltage adjustment values,
wherein the step of obtaining the test read voltages comprises:
obtaining a second test read voltage among the test read voltages by adjusting a first test read voltage among the test read voltages according to a first voltage adjustment value corresponding to the first test read voltage, and obtaining a third test read voltage among the test read voltages by adjusting the second test read voltage according to a second voltage adjustment value corresponding to the second test read voltage, wherein the first test read voltage is a preset test read voltage, the first voltage adjustment value is a preset voltage adjustment value, and the first voltage adjustment value is different from the second voltage adjustment value.

2. The read voltage tracking method according to claim 1 , wherein the step of obtaining the test read voltages further comprises:
reading first data by applying the first test read voltage to a plurality of first memory cells among the memory cells, and calculating a first quantity of memory cells identified as in a first state among the first memory cells according to the first data;
reading second data by applying the second test read voltage to the first memory cells, and calculating a second quantity of memory cells identified as in the first state among the first memory cells according to the second data;
obtaining a first discrepancy value according to the first quantity and the second quantity; and
deciding the second voltage adjustment value according to the first discrepancy value.

3. The read voltage tracking method according to claim 2 , wherein the step of obtaining the first discrepancy value according to the first quantity and the second quantity comprises:
calculating a numerical difference between the first quantity and the second quantity; and
obtaining the first discrepancy value by calculating a ratio of the numerical difference to the first voltage adjustment value.

4. The read voltage tracking method according to claim 2 , wherein the step of obtaining the optimal read voltage from the test read voltages according to the voltage adjustment values comprises:
determining whether the first discrepancy value is a minimal discrepancy value; and
setting the second test read voltage to be the optimal read voltage when determining that the first discrepancy value is the minimal discrepancy value.

5. The read voltage tracking method according to claim 2 , wherein the step of obtaining the test read voltages further comprises:
reading third data by applying the third test read voltage to the first memory cells, and calculating a third quantity of memory cells identified as in the first state among the first memory cells according to the third data;
obtaining a second discrepancy value according to the second quantity and the third quantity; and
deciding a third voltage adjustment value corresponding to the third test read voltage according to the second discrepancy value,
wherein the first discrepancy value is greater than the second discrepancy value, and the second voltage adjustment value is greater than the third voltage adjustment value.

6. The read voltage tracking method according to claim 2 , further comprising:
setting a voltage adjustment threshold,
wherein the step of deciding the second voltage adjustment value according to the first discrepancy value comprises:
deciding the second voltage adjustment value to be the voltage adjustment threshold if the second voltage adjustment value is greater than the voltage adjustment threshold.

7. A memory storage device, comprising:
a connection interface unit, configured to couple to a host system;
a rewritable non-volatile memory module comprising a plurality of memory cells;
a memory control circuit unit, coupled to the connection interface unit and the rewritable non-volatile memory module,
wherein the memory control circuit unit is configured to obtain a plurality of test read voltages, wherein the test read voltages correspond to a plurality of voltage adjustment values,
wherein the memory control circuit unit is configured to obtain an optimal read voltage from the test read voltages according to the voltage adjustment values,
wherein in the operation of obtaining the test read voltages, the memory control circuit unit is configured to obtain a second test read voltage among the test read voltages by adjusting a first test read voltage among the test read voltages according to a first voltage adjustment value corresponding to the first test read voltage and obtain a third test read voltage among the test read voltages by adjusting the second test read voltage according to a second voltage adjustment value corresponding to the second test read voltage, wherein the first test read voltage is a preset test read voltage, the first voltage adjustment value is a preset voltage adjustment value, and the first voltage adjustment value is different from the second voltage adjustment value.

8. The memory storage device according to claim 7 , wherein in the operation of obtaining the test read voltages, the memory control circuit unit is further configured to give a read command sequence which instructs to read first data by applying the first test read voltage to a plurality of first memory cells among the memory cells and calculate a first quantity of memory cells identified as in a first state among the first memory cells according to the first data,
wherein in the operation of obtaining the test read voltages, the memory control circuit unit is further configured to give another read command sequence which instructs to read second data by applying the second test read voltage to the first memory cells and calculate a second quantity of memory cells identified as in the first state among the first memory cells according to the second data,
wherein in the operation of obtaining the test read voltages, the memory control circuit unit is further configured to obtain a first discrepancy value according to the first quantity and the second quantity and decide the second voltage adjustment value according to the first discrepancy value.

9. The memory storage device according to claim 8 , wherein in the operation of obtaining the first discrepancy value according to the first quantity and the second quantity, the memory control circuit unit is configured to calculate a numerical difference between the first quantity and the second quantity and obtain the first discrepancy value by calculating a ratio of the numerical difference to the first voltage adjustment value.

10. The memory storage device according to claim 8 , wherein in the operation of obtaining the optimal read voltage from the test read voltages according to the voltage adjustment values, the memory control circuit unit is configured to determine whether the first discrepancy value is a minimal discrepancy value, and the memory control circuit unit is configured to set the second test read voltage to be the optimal read voltage when determining that the first discrepancy value is the minimal discrepancy value.

11. The memory storage device according to claim 8 , wherein in the operation of obtaining the test read voltages, the memory control circuit unit is further configured to give another read command sequence which in

Assignees

• Phison Electronics Corp

Inventors

• Lin Wei
• Hsu Yu Cheng
• Liu An Cheng

Classifications

• G11C16/10

  Programming or data input circuits · CPC title

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title

• G11C29/12

  Built-in arrangements for testing, e.g. built-in self testing [BIST] {or interconnection details} · CPC title

• G11C16/3427 Primary

  Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written · CPC title

• G11C16/14

  Circuits for erasing electrically, e.g. erase voltage switching circuits · CPC title