Classification of error rate of data retrieved from memory cells

Patent metadata

Field	Value
Publication number	US-12009034-B2
Application number	US-202016807065-A
Country	US
Kind code	B2
Filing date	Mar 2, 2020
Priority date	Mar 2, 2020
Publication date	Jun 11, 2024
Grant date	Jun 11, 2024

Abstract

A memory sub-system configured to: measure a plurality of sets of signal and noise characteristics of a group of memory cells in a memory device; determine a plurality of optimized read voltages of the group of memory cells from the plurality of sets of signal and noise characteristics respectively; generate features from the plurality of sets of signal and noise characteristics, including at least one compound feature generated from the plurality of sets of signal and noise characteristics; generate, using the features, a classification of a bit error rate of data retrievable from the group of memory cells; and control an operation to read the group of memory cells based on the classification.

First claim

What is claimed is:

1. A memory device, comprising:
a plurality of groups of memory cells formed on an integrated circuit die;
a calibration circuit configured to measure signal and noise characteristics of a group of memory cells to generate features as input to a decision tree; and
a data integrity classifier configured to determine a classification of a bit error rate of data retrievable from the group of memory cells by applying the features to the decision tree, wherein the data integrity classifier includes:
a set of feature registers configured to store the features;
a comparator;
a selection logic configured to select at least one feature from the feature registers as input to the comparator;
a leaf path register file configured to store data identifying node connectivity in the decision tree; and
a leaf selection logic configured to control the selection logic based on an output of the comparator and the data stored in the leaf path register file, and to provide the classification in response to reaching a leaf node in the decision tree;

wherein the memory device is configured to control an operation to read the group of memory cells based on the classification.

2. The memory device of claim 1 , wherein the decision tree is a binary classification decision tree.

3. The memory device of claim 1 , wherein the data integrity classifier further includes:
a set of threshold registers configured to store pre-defined thresholds;
wherein the selection logic is configured to select a threshold from the set of threshold registers as input to the comparator.

4. The memory device of claim 3 , wherein the data integrity classifier further comprises:
a plurality of term selection register sets;
wherein the leaf selection logic is configured to use the plurality of term selection register sets to control the selection logic in selecting a plurality of terms respectively; and
wherein the comparator is configured to generate the output based on the plurality of terms.

5. The memory device of claim 4 , wherein the output of the comparator is based on whether or not a predefined relation is met by the plurality of terms.

6. The memory device of claim 5 , wherein the data integrity classifier is configured to evaluate the decision tree one node at a time.

7. The memory device of claim 6 , further comprising:
an integrated circuit package enclosing the memory device.

8. The memory device of claim 5 , further comprising:
a feature generator; and
wherein the calibration circuit is configured to measure a plurality of sets of signal and noise characteristics and determine a plurality of read voltages optimized based on the plurality of sets of signal and noise characteristics respectively;
wherein the calibration circuit is configured to measure a second set of signal and noise characteristics after measuring first sets of signal and noise characteristics; and
wherein the feature generator is configured to:
generate a first compound feature from the first sets of signal and noise characteristics, at least in part in parallel with measuring the second set; and
update the first compound feature according to the second set of signal and noise characteristics after the second set becomes available.

9. A method, comprising:
storing, in feature registers of a data integrity classifier, features generated from signal and noise characteristics of a group of memory cells in a memory device;
storing, in a leaf path register file, the data identifying node connectivity in a decision tree of the data integrity classifier; and
determining a classification that characterizes a bit error rate of data retrievable from the group of memory cells in the memory device via evaluation of the decision tree, wherein the determining of the classification comprises:
selecting, from the feature registers, at least one feature as an input, the at least one feature generated from signal and noise characteristics of the group of memory cells in the memory device, wherein the input is provided to generate outputs in selecting child nodes in the decision tree;
generating an output based at least in part on the at least one feature selected from the feature registers, the output identifying a selected child node in the decision tree;
controlling further selecting from the feature registers in evaluating the child node according to the data identifying the node connectivity in the decision tree, wherein the further selecting is controlled according to the data identifying the node connectivity in the decision tree; and
providing the classification pre-associated with a leaf node in response to an output that selects the leaf node according to the data identifying the node connectivity in the decision tree.

10. The method of claim 9 ,
wherein the determining of the classification includes evaluation of the decision tree using a node decision logic and a leaf selection logic.

11. The method of claim 9 , further comprising:
controlling an operation to read the group of memory cells based on the classification.

12. The method of claim 11 , wherein the method further comprises:
storing pre-defined thresholds in a set of threshold registers of the data integrity classifier; and
selecting a threshold from the threshold registers as input to a comparator;
wherein the outputs generated are a function of the threshold selected from the threshold registers and the at least one feature selected from the feature registers.

13. The method of claim 12 , further comprising:
storing in a plurality of term selection register sets, each register in the plurality of term selection register sets identifying, for a branch node in the decision tree, a term stored in the threshold registers and the feature registers;
wherein the plurality of term selection register sets are configured to provide, for the branch node, a plurality of outputs that are used to select a plurality of terms respectively from the threshold registers and the feature registers; and
wherein the plurality of terms are provided as input to generate an output.

14. The method of claim 13 , wherein the decision tree is a binary classification decision tree.

15. The method of claim 13 , wherein branch nodes in the decision tree are evaluated one at a time until the leaf node is reached in the decision tree.

16. The method of claim 15 , further comprising:
measuring a plurality of sets of signal and noise characteristics, including first sets of signal and noise characteristics, and a second set of signal and noise characteristics measured after measuring the first sets of signal and noise characteristics;
calculating a plurality of read voltages optimized based on the plurality of sets of signal and noise characteristics respectively;
generating a first compound feature from the first sets of signal and noise characteristics, at least in part in parallel with measuring the second set; and
updating the first compound feature according to the second set of signal and noise characteristics after the second set becomes available, wherein at least one feature stored in the feature registers is based on the first compound feature.

17. A memory sub-system, comprising:
a processing device; and
at least one memory device, the memory device having:
a group of memory cells formed on an integrated circuit die; and
a calibration circuit configured to measure a plurality of sets of signal and noise characteristics of the group of memory cells and determine a plurality of optimized read voltages of the group of memory cells from

Assignees

• Micron Technology Inc

Inventors

• Parthasarathy Sivagnanam
• Fitzpatrick James
• Khayat Patrick Robert
• Alhussien Abdelhakim S

Classifications

• G11C16/26 Primary

  Sensing or reading circuits; Data output circuits · CPC title

• H03M13/612 Primary

  Aspects specific to channel or signal-to-noise ratio estimation (H03M13/63 takes precedence) · CPC title

• G06F18/24323 Primary

  Tree-organised classifiers · CPC title

• G06F9/30101

  Special purpose registers · CPC title

• G06F9/30021

  Compare instructions, e.g. Greater-Than, Equal-To, MINMAX · CPC title