Memory controller and operating method thereof

Patent metadata

Field	Value
Publication number	US-9564239-B2
Application number	US-201615071986-A
Country	US
Kind code	B2
Filing date	Mar 16, 2016
Priority date	Mar 16, 2015
Publication date	Feb 7, 2017
Grant date	Feb 7, 2017

Abstract

A method for operating a memory controller includes: performing a hard decision read operation to read hard decision data from a memory device; if a hard decoding for the hard decision data fails, assigning log likelihood ratio (LLR) values to cells falling in a plurality of voltage regions corresponding to a plurality of read reference voltages; performing a soft decision read operation based on the LLR values and a soft decoding for the soft decision data to generate an error free data; performing a read operation to read data from the memory device using each of the plurality of read reference voltages to generate raw data for each of the plurality of read reference voltages; and determining an optimal read reference voltage among the plurality of the read reference voltages based on the raw data and the error free data.

First claim

What is claimed is:

1. A method comprising:
performing a hard decision read operation to read hard decision data from a memory device;
if a hard decoding for the hard decision data fails, assigning log likelihood ratio (LLR) values to cells falling in a plurality of voltage regions corresponding to a plurality of read reference voltages;
performing a soft decision read operation based on the LLR values and a soft decoding for the soft decision data to generate an error free data;
performing a read operation to read data from the memory device using each of the plurality of read reference voltages to generate raw data for each of the plurality of read reference voltages; and
determining an optimal read reference voltage among the plurality of the read reference voltages based on the raw data and the error free data.

2. The method of claim 1 , wherein determining of the optimal read reference voltage comprises:
comparing the raw data with the error free data;
calculating the total number of errors for the raw data based on the comparison result; and
selecting a read reference voltage with the minimum number of errors among the plurality of the read reference voltages as the optimal read reference voltage.

3. The method of claim 2 , wherein comparing of the raw data with the error free data comprises;
performing an exclusive-OR (XOR) operation both the raw data and the error free data to generate XORed data.

4. The method of claim 3 , wherein the XORed data includes a plurality of bit locations, and
wherein calculating of the total number of errors for the raw data comprises counting at least one error bit in the bit locations of the XORed data.

5. The method of claim 1 , further comprising:
determining whether the hard decoding for the hard decision data fails.

6. A method comprising:
performing a soft decision read operation for cells from a memory device, falling in a plurality of voltage regions within a predetermined region corresponding to a plurality of read reference voltages;
performing a soft decoding for the soft decision data to generate an error free data;
performing a read operation using each of the plurality of read reference voltages to generate raw data for each of the plurality of read reference voltages; and
determining an optimal read reference voltage among the plurality of the read reference voltages based on the raw data and the error free data.

7. The method of claim 6 , wherein determining of the optimal read reference voltage comprises:
comparing the raw data with the error free data;
calculating the total number of errors for the raw data based on the comparison result; and
selecting a read reference voltage with the minimum number of errors among the plurality of the read reference voltages as the optimal read reference voltage.

8. The method of claim 7 , wherein comparing of the raw data with the error free data comprises performing an exclusive-OR (XOR) operation both the raw data and the error free data to generate XORed data.

9. The method of claim 8 , wherein the XORed data includes a plurality of bit locations, and
wherein calculating of the total number of errors for the raw data comprises counting at least one error bit in the bit locations of the XORed data.

10. The method of claim 6 , further comprising:
performing a hard decision read operation to read hard decision data from the memory device,
wherein the performing of the soft decision read operation is performed, if a hard decoding for the hard decision data fails.

11. A controller for controlling a memory device, comprising:
a first read processing unit suitable for performing a hard decision read operation to read hard decision data from the memory device;
a second read processing unit suitable for, if a hard decoding for the hard decision data fails, assigning log likelihood ratio (LLR) values to cells falling in a plurality of voltage regions corresponding to a plurality of read reference voltages, and performing a read operation to read data from the memory device using each of the plurality of read reference voltages to generate raw data for each of the plurality of read reference voltages;
a third read processing unit suitable for performing a soft decision read operation based on the LLR values and a soft decoding for the soft decision data to generate an error free data; and
a determiner suitable for determining an optimal read reference voltage among the plurality of the read reference voltages based on the raw data and the error free data.

12. The controller of claim 11 , wherein the determiner is suitable for:
comparing the raw data with the error free data;
calculating the total number of errors for the raw data based on the comparison result; and
selecting a read reference voltage with the minimum number of errors among the plurality of the read reference voltages as the optimal read reference voltage.

13. The controller of claim 12 , wherein the determiner is suitable for comparing the raw data with the error free data by performing an exclusive-OR (XOR) operation both the raw data and the error free data to generate XORed data.

14. The controller of claim 13 , wherein the XORed data includes a plurality of bit locations, and
wherein the determiner is suitable for calculating the total number of errors for the raw data by counting at least one error bit in the bit locations of the XORed data.

15. The controller of claim 11 , wherein the first read processing unit is further suitable for determining whether the hard decoding for the hard decision data fails.

16. A controller for controlling a memory device, comprising:
a first unit suitable for performing a soft decision read operation for cells from a memory device, falling in a plurality of voltage regions within a predetermined region corresponding to a plurality of read reference voltages and a soft decoding for the soft decision data to generate an error free data;
a second unit suitable for performing a read operation using each of the plurality of read reference voltages to generate raw data for each of the plurality of read reference voltages; and
a determiner suitable for determining an optimal read reference voltage among the plurality of the read reference voltages based on the raw data and the error free data.

17. The controller of claim 16 , wherein the determiner is suitable for comparing the raw data with the error free data;
calculating the total number of errors for the raw data based on the comparison result; and
selecting a read reference voltage with the minimum number of errors among the plurality of the read reference voltages as the optimal read reference voltage.

18. The controller of claim 17 , wherein the determiner is suitable for comparing the raw data with the error free data by performing an exclusive-OR (XOR) operation both the raw data and the error free data to generate XORed data.

19. The controller of claim 18 , wherein the XORed data includes a plurality of bit locations, and
wherein the determiner is suitable for calculating the total number of errors for the raw data by counting at least one error bit in the bit locations of the XORed data.

20. The controller of claim 16 , further comprising:
a third unit suitable for performing a hard decision read operation to read hard decision data from the memory device,
wherein the first unit is suitable for performing the soft decision read operation, if a hard decoding for the hard decision data fails.

Assignees

• Sk Hynix Memory Solutions Inc

Inventors

• Cai Yu
• Yen Johnson
• Chu Ngok Ying

Classifications

• G11C16/3404 Primary

  Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells · CPC title

• G11C16/28 Primary

  using differential sensing or reference cells, e.g. dummy cells · CPC title

• G11C29/028

  with adaption or trimming of parameters · CPC title

• G11C29/021

  in voltage or current generators · CPC title

• G11C16/26 Primary

  Sensing or reading circuits; Data output circuits · CPC title