Semiconductor protection device

Patent metadata

Field	Value
Publication number	US-12002890-B2
Application number	US-202217585284-A
Country	US
Kind code	B2
Filing date	Jan 26, 2022
Priority date	May 21, 2021
Publication date	Jun 4, 2024
Grant date	Jun 4, 2024

Abstract

A semiconductor protection device includes: an N-type epitaxial layer, a device isolation layer disposed in the N-type epitaxial layer, an N-type drift region disposed below the device isolation layer, an N-type well disposed in the N-type drift region, first and second P-type drift regions, respectively disposed to be in contact with the device isolation layer, and spaced apart from the N-type drift region, first and second P-type doped regions, respectively disposed in the first and second P-type drift regions, first and second N-type floating wells, respectively disposed in the first and second P-type drift regions to be spaced apart from the first and second P-type doped regions, and disposed to be in contact with the device isolation layer, and first and second contact layer, respectively disposed to cover the first and second N-type floating well, to be in contact with the device isolation layer.

First claim

What is claimed is:

1. A semiconductor protection device comprising:
an N-type buried layer on a P-type substrate;
an N-type epitaxial layer on the N-type buried layer;
a device isolation layer on an upper surface of the N-type epitaxial layer;
an N-type drift region below the device isolation layer;
an N-type well in the N-type drift region;
first and second P-type drift regions, each of the first and second P-type drift regions in contact with a respective opposite end of the device isolation layer and spaced apart from the N-type drift region;
first and second high voltage P-type wells below the first and second P-type drift regions and in contact with the N-type buried layer;
first and second P-type wells, each of the first and second P-type wells in a respective one of the first and second P-type drift regions;
first and second N-type floating wells, each of the first and second N-type floating wells in the respective one of the first and second P-type drift regions and spaced apart from a respective one of the first and second P-type wells, and wherein each of the first and second N-type floating wells is in contact with the respective one of the opposite ends of the device isolation layer;
first and second P-type doped regions, each of the first and second P-type doped regions in the respective one of the first and second P-type wells;
a first contact layer on the N-type epitaxial layer and in contact with the first N-type floating well and the device isolation layer;
a second contact layer on the N-type epitaxial layer and in contact with the second N-type floating well and the device isolation layer;
a cathode electrode on the first P-type doped region and spaced apart from the first contact layer; and
an anode electrode on the second P-type doped region and spaced apart from the second contact layer.

2. The semiconductor protection device of claim 1 , wherein each of the first and second N-type floating wells is below the device isolation layer.

3. The semiconductor protection device of claim 1 , wherein a lower surface of the N-type well and lower surfaces of the first and second N-type floating wells have a same width.

4. The semiconductor protection device of claim 1 , wherein the N-type well and the first and second N-type floating wells are doped with the same N-type impurities.

5. The semiconductor protection device of claim 1 , wherein the first and second N-type floating wells are doped at the same impurity concentration.

6. The semiconductor protection device of claim 1 , further comprising:
an N-type doped region in the device isolation layer, wherein the N-type doped region is in contact with an upper surface of the N-type epitaxial layer and the N-type well, and
wherein a thickness of the N-type doped region is less than a thickness of the device isolation layer.

7. The semiconductor protection device of claim 1 , wherein the first and second contact layers comprise a material including at least one of polysilicon, tungsten, and aluminum.

8. The semiconductor protection device of claim 1 , wherein the first and second P-type doped regions do not overlap the first and second contact layers.

9. A semiconductor protection device comprising:
an N-type epitaxial layer;
a device isolation layer on an upper surface of the N-type epitaxial layer;
an N-type drift region below the device isolation layer;
an N-type well in the N-type drift region;
first and second P-type drift regions, each of the first and second P-type drift regions in contact with a respective opposite end of the device isolation layer, and spaced apart from the N-type drift region;
first and second P-type doped regions, each of the first and second P-type doped regions in a respective one of the first and second P-type drift regions;
first and second N-type floating wells, each of the first and second N-type floating wells in the respective one of the first and second P-type drift regions and spaced apart from a respective one of the first and second P-type doped regions, and wherein each of the first and second N-type floating wells is in contact with the respective one of the opposite ends of the device isolation layer;
a first contact layer on the N-type epitaxial layer and in contact with the first N-type floating well and the device isolation layer; and
a second contact layer on the N-type epitaxial layer and in contact with the second N-type floating well and the device isolation layer.

10. The semiconductor protection device of claim 9 , further comprising:
first and second P-type wells, each of the first and second P-type wells in the respective one of the first and second P-type drift regions, and wherein the first and second P-type wells each overlap the respective one of the first and second P-type doped regions.

11. The semiconductor protection device of claim 10 , wherein the first P-type doped region is in the first P-type well, and wherein the second P-type doped region is in the second P-type well.

12. The semiconductor protection device of claim 9 , wherein the first and second N-type floating wells are mirror-symmetrical with respect to the N-type well.

13. The semiconductor protection device of claim 9 , wherein the first and second N-type floating wells are in contact with the device isolation layer.

14. The semiconductor protection device of claim 9 , wherein the first and second N-type floating wells are doped at a similar impurity concentration as the N-type well.

15. A semiconductor protection device comprising:
a first conductivity-type epitaxial layer comprising first and second regions, wherein the first region comprises:
a device isolation layer on an upper surface of the first conductivity-type epitaxial layer, wherein the device isolation layer overlaps a central axis of the semiconductor protection device;
a first conductivity-type drift region below the device isolation layer;
a first conductivity-type well in the first conductivity-type drift region;
a second conductivity-type drift region in contact with the device isolation layer and spaced apart from the first conductivity-type drift region;
a high voltage second conductivity-type well below the second conductivity-type drift region;
a second conductivity-type doped region in the second conductivity-type drift region;
a first conductivity-type floating well spaced apart from the second conductivity-type doped region in the second conductivity-type drift region;
a contact layer on the first conductivity-type epitaxial layer, wherein the contact layer overlaps the first conductivity-type floating well and is in contact with the device isolation layer; and
an electrode on the second conductivity-type doped region and spaced apart from the contact layer, and
wherein the second region and the first region are mirror-symmetrical.

16. The semiconductor protection device of claim 15 , further comprising:
a first conductivity-type doped region in contact with the first conductivity-type well at the central axis.

17. The semiconductor protection device of claim 15 , wherein the first conductivity-type floating well is spaced apart from the device isolation layer.

18. The semiconductor protection device of claim 15 , wherein the first conductivity-type floating well is in contact with the device isolation layer.

19. The semiconductor protection device of claim 15 , wherein the first conductivity-type floating well does not overlap the contact layer.

20. The semiconductor protection device of claim 15 , wherei

Assignees

• Samsung Electronics Co Ltd

Inventors

• Yoo Jaehyun
• Lee Kyuok
• Kwon Uihui
• Kim Junhyeok
• Jeon Yongwoo
• Jeong Dawon
• Ko Jaehyok

Classifications

• H10D62/111

  Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures · CPC title

• H10D62/051

  Forming charge compensation regions, e.g. superjunctions · CPC title

• H10D62/114 Primary

  PN junction isolations · CPC title

• H10D62/115

  Dielectric isolations, e.g. air gaps · CPC title

• H10D64/112

  comprising multiple field plate segments · CPC title