Low capacitance bidirectional transient voltage suppressor

Patent metadata

Field	Value
Publication number	US-10937780-B2
Application number	US-201916447704-A
Country	US
Kind code	B2
Filing date	Jun 20, 2019
Priority date	May 25, 2017
Publication date	Mar 2, 2021
Grant date	Mar 2, 2021

Abstract

A bidirectional transient voltage suppressor (TVS) circuit for data pins of electronic devices includes two sets of steering diodes and a diode triggered clamp device in some embodiment. In other embodiments, a bidirectional transient voltage suppressor (TVS) circuit for data pins of electronic devices includes two sets of steering diodes with a clamp device merged with a steering diode in each set. The TVS circuit is constructed to realize low capacitance at the protected nodes and improved clamping voltage for robust protection against surge evens. In some embodiments, the TVS circuit realizes low capacitance at the protected nodes by fully or almost completely depleting the P-N junction connected to the protected nodes in the operating voltage range. In this manner, the TVS circuit does not present undesirable parasitic capacitance to the data pins being protected, especially when the data pins are applied in high speed applications.

First claim

What is claimed is:

1. A bidirectional transient voltage suppressing (TVS) device comprising:
a semiconductor layer comprising a first epitaxial layer of a first conductivity type, a first buried layer of a second conductivity type, opposite to the first conductivity type, formed on the first epitaxial layer in selected areas, and a second epitaxial layer of the first conductivity type formed on the first buried layer and the first epitaxial layer;
a plurality of active regions formed in the semiconductor layer, the active regions being isolated from each other by isolation structures;
a first diode formed in a first active region of the plurality of active regions, the first active region being formed in an area of the semiconductor layer comprising the first buried layer, the first diode comprising a first region of the second conductivity type formed in the second epitaxial layer, the second epitaxial layer being an anode and the first region being a cathode of the first diode, wherein the first region, the first buried layer and the first and second epitaxial layers in the first active region are depleted at a bias voltage of zero volt, reducing a vertical parasitic capacitance at the anode of the first diode; and
a merged diode/clamp device formed in a second active region of the plurality of active regions and comprising a second diode integrated with a silicon controlled rectifier (SCR), the second diode having a cathode being formed in a second region of the second conductivity type formed in the second epitaxial layer and having an anode being formed in a third region of the first conductivity type formed in the second epitaxial layer adjacent the second region, and the SCR having an anode formed in a fourth region formed in the second region, a cathode, and a gate, wherein the second region and the first and second epitaxial layers in the second active region are depleted at a bias voltage of zero volt, reducing a vertical parasitic capacitance at the anode of the second diode,
wherein the cathode of the second diode is coupled to a first protected node and the cathode of the first diode is coupled to a second protected node, the cathode of the second diode is coupled to the anode of the SCR and the anode of the first diode is coupled to the cathode of the SCR, and wherein in response to a voltage applied to one of the protected nodes exceeding a first voltage level, the SCR conducts and clamps the voltage at the respective protected node at a clamping voltage.

2. The bidirectional TVS device of claim 1 , wherein
the second region of the merged diode/clamp device comprises a first well of the second conductivity type formed in the second epitaxial layer;
the third region of the merged diode/clamp device comprises a second well of the first conductivity type formed in the second epitaxial layer adjacent the first well, the second well forming the gate of the SCR;
a fifth region of the second conductivity type formed in contact with the first and second wells; and
a sixth region of the second conductivity type formed in the second well, the sixth region forming the cathode of the SCR.

3. The bidirectional TVS device of claim 1 , further comprising:
a second buried layer of the second conductivity type formed in the second active region of the semiconductor layer, the second epitaxial layer being formed above the second buried layer, wherein the second buried layer is depleted at a bias voltage of zero volt.

4. The bidirectional TVS device of claim 3 , wherein the second region of the merged diode/clamp device comprises a first well of the second conductivity type formed in the second epitaxial layer above the second buried layer; and
the third region of the merged diode/clamp device comprises a second well of the first conductivity type formed in the second epitaxial layer above the second buried layer and adjacent the first well, the second well forming the gate of the SCR;
a fifth region of the second conductivity type formed in contact with the first and second wells; and
a sixth region of the second conductivity type formed in the second well, the sixth region forming the cathode of the SCR.

5. The bidirectional TVS device of claim 1 , wherein the first region comprises a heavily doped region of the second conductivity type formed in a lightly doped region of the second conductivity type, the lightly doped region and the first buried layer being provided to deplete the first and second epitaxial layers at the bias voltage of zero volt.

6. The bidirectional TVS device of claim 1 , wherein the first diode further comprises a seventh region of the first conductivity type and being formed in the second epitaxial layer and spaced apart from the first region.

7. The bidirectional TVS device of claim 1 , further comprising a semiconductor substrate of the first conductivity type and being heavily doped, the semiconductor layer being formed on the semiconductor substrate.

8. The bidirectional TVS device of claim 1 , wherein each of the isolation structures comprises an oxide filled trench isolation structure.

9. The bidirectional TVS device of claim 1 , wherein each of the isolation structures comprises a trench isolation structure, each trench being lined with an oxide layer and filled with a polysilicon layer.

10. The bidirectional TVS device of claim 1 , wherein the first conductivity type comprises P-type conductivity and the second conductivity type comprises N-type conductivity.

Assignees

• Alpha & Omega Semiconductor Cayman Ltd

Inventors

• Mallikarjunaswamy Shekar
• Shi Ning

Classifications

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10D62/129

  Cathode regions of diodes · CPC title

• H10D89/611

  using diodes as protective elements · CPC title

• H10D62/115

  Dielectric isolations, e.g. air gaps · CPC title

• H10D8/411

  PN diodes having planar bodies · CPC title