Semiconductor devices including a lateral bipolar structure with high current gains

Patent metadata

Field	Value
Publication number	US-9190501-B2
Application number	US-201313800063-A
Country	US
Kind code	B2
Filing date	Mar 13, 2013
Priority date	Feb 26, 2013
Publication date	Nov 17, 2015
Grant date	Nov 17, 2015

Abstract

A semiconductor device includes an emitter region, a collector region and a base region. The emitter region is implanted in a semiconductor substrate. The collector region is implanted in the semiconductor substrate. The base region is disposed between the emitter region and collector region. The base region includes no more than one LDD region and no more than one halo region. The base region contacts directly with at least one of the emitter region and the collector region.

First claim

What is claimed is:

1. A lateral bipolar transistor, comprising:
an emitter region disposed in a semiconductor substrate, the emitter region having an upper emitter surface;
a collector region disposed in the semiconductor substrate, the collector region laterally disposed along a common surface from the upper emitter surface;
a base region between the emitter region and collector region; and
a first lightly doped drain (LDD) region disposed in the base region and adjacent to the emitter region, the first LDD region disposed directly below a gate structure,
where the base region contacts directly with the collector region without a second LDD region adjacent to the collector region.

2. The lateral bipolar transistor of claim 1 , further comprising a halo region disposed in the base region and adjacent to the emitter region.

3. The lateral bipolar transistor of claim 1 , further comprising a gate structure disposed on the base region, wherein the gate structure is disposed between a first spacer and a second spacer respectively disposed on the emitter region and the collector region.

4. The lateral bipolar transistor of claim 1 , wherein a spacer is disposed adjacent to the emitter region and in contact with the gate structure and separate the gate structure from the emitter region.

5. The lateral bipolar transistor of claim 1 , further comprising a N well adjacent to the collector.

6. The lateral bipolar transistor of claim 5 , further comprising a deep N well disposed in the semiconductor substrate and directly below the base region.

7. The lateral bipolar transistor of claim 5 , wherein the emitter region and the collector region are doped with an n-type material and the base region is doped with a p-type material.

8. The lateral bipolar transistor of claim 7 , wherein the emitter region and the collector region are doped with a p-type material and the base region is doped with an n-type material.

9. A lateral bipolar transistor, comprising:
an emitter region disposed in a semiconductor substrate, the emitter region having an upper emitter surface;
a collector region disposed in the semiconductor substrate, the collector region laterally disposed along a common surface from the upper emitter surface;
a base region between the emitter region and collector region;
a gate structure disposed on the base region; and
a halo region below a first lightly doped drain (LDD) region disposed in the base region, the halo region and the first LDD region in direct contact with the emitter, the first LDD region disposed directly below the gate structure without a second LDD region adjacent to the collector region.

10. The lateral bipolar transistor of claim 9 , wherein the emitter region and the collector region are doped with an n-type material and the base region is doped with a p-type material.

11. The lateral bipolar transistor of claim 9 , wherein the emitter region and the collector region are doped with a p-type material and the base region is doped with an n-type material.

12. The lateral bipolar transistor of claim 9 , wherein the gate structure is disposed between the emitter region and the collector region.

13. The lateral bipolar transistor of claim 12 , further comprising a N well adjacent to the collector.

14. The lateral bipolar transistor of claim 12 , further comprising a deep N well disposed in the semiconductor substrate and directly below the base region.

15. The lateral bipolar transistor of claim 14 , wherein an average half-pitch in the lateral bipolar transistor is less than 30 nm.

16. The lateral bipolar transistor of claim 15 , wherein the lateral bipolar transistor supports a current gain up to at least 30.

17. A lateral bipolar transistor, comprising:
an emitter region disposed in a semiconductor substrate, the emitter region having an upper emitter surface;
a collector region disposed in the semiconductor substrate , the collector region laterally disposed along a common surface from the upper emitter surface;
a base region between the emitter region and collector region; and
a gate structure on the base region,
wherein:
the base region comprises a first lightly doped drain (LDD) region adjacent to the emitter region, the first LDD region in direct contact with the gate structure without a second LDD region adjacent to the collector region; and
the base region comprises an L-shaped well partially under the collector region.

18. The lateral bipolar transistor of claim 17 , wherein the gate structure is disposed directly on the L-shaped well.

19. The lateral bipolar transistor of claim 18 , wherein the L-shaped well is an N well partially under the gate structure.

20. The lateral bipolar transistor of claim 19 , further comprising a shallow trench isolation (STI) region that directly contacts both the L-shaped well and the collector.

Assignees

• Broadcom Corp

Inventors

• Ito Akira
• Yau Kenneth

Classifications

• H10D12/00

  Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT] · CPC title

• H10D62/137

  Collector regions of BJTs · CPC title

• H10D62/134

  of lateral BJTs · CPC title

• H10D10/061

  of lateral BJTs  (of heterojunction BJTs H10D10/021; of thin film BJTs H10D10/041) · CPC title

• H10D10/60 Primary

  Lateral BJTs · CPC title