Fan-out type semiconductor package and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-12002798-B2
Application number	US-202217861359-A
Country	US
Kind code	B2
Filing date	Jul 11, 2022
Priority date	Jan 2, 2020
Publication date	Jun 4, 2024
Grant date	Jun 4, 2024

Abstract

A fan-out type semiconductor package may include a frame, an upper chip stack, a first redistribution pattern, a lower chip stack, a second redistribution pattern and a redistribution post. The frame may have a cavity. The upper chip stack may be arranged in the cavity. The first redistribution pattern may be arranged under the frame. The first redistribution pattern may be electrically connected with the upper chip stack. The lower chip stack may be arranged under the first redistribution pattern. The second redistribution pattern may be arranged under the lower chip stack. The second redistribution pattern may be electrically connected with the lower chip stack. The redistribution post may be electrically connected between the first redistribution pattern and the second redistribution pattern. Thus, the fan-out type semiconductor package may have an improved heat dissipation characteristic with a thin thickness.

First claim

What is claimed is:

1. A method of manufacturing a fan-out type semiconductor package, the method comprising:
arranging an upper chip stack in a cavity of a frame;
forming a first redistribution pattern under the frame, the first redistribution pattern electrically connected with the upper chip stack;
arranging a lower chip stack under the first redistribution pattern;
forming a second redistribution pattern under the lower chip stack, the second redistribution pattern electrically connected with the lower chip stack; and
electrically connecting the first redistribution pattern and the second redistribution pattern with each other using a redistribution post,
wherein arranging the upper chip stack in the cavity comprises stacking a second upper chip, which has a size substantially the same as a size of a first upper chip, on an upper surface of the first upper chip in a step-like shape to expose a first upper pad on an edge portion of the first upper chip, which is not overlapped with the second upper chip, and to expose a second upper pad on an edge portion of the second upper chip, which is not overlapped with the first upper chip.

2. The method of claim 1 , wherein electrically connecting the upper chip stack with the first redistribution pattern comprises:
downwardly extending a first upper post from the first upper pad, the first upper post connected to the first redistribution pattern; and
downwardly extending a second upper post from the second upper pad, the second upper post connected to the first redistribution pattern.

3. The method of claim 1 , wherein arranging the upper chip stack in the cavity comprises stacking the second upper chip on the upper surface of the first upper chip in a pyramidal step-like shape to expose two adjacent edge portions of the first upper chip, which are not overlapped with the second upper chip, and to expose two adjacent edge portions of the second upper chip, which are not overlapped with the first upper chip.

4. The method of claim 1 , wherein arranging the lower chip stack under the first redistribution pattern comprises stacking a second lower chip, which has a size substantially the same as a size of a first lower chip, on an upper surface of the first lower chip in a step-like shape to expose a first lower pad on an edge portion of the first lower chip, which is not overlapped with the second lower chip, and to expose a second lower pad on an edge portion of the second lower chip, which is not overlapped with the first lower chip.

5. The method of claim 4 , wherein electrically connecting the lower chip stack with the second redistribution pattern comprises:
downwardly extending a first lower post from the first lower pad, the first lower post connected to the second redistribution pattern; and
downwardly extending a second lower post from the second lower pad, the second lower post connected to the second redistribution pattern.

6. The method of claim 3 , wherein arranging the upper chip stack in the cavity comprises stacking the second lower chip on the upper surface of the first lower chip in a pyramidal step-like shape to expose two adjacent edge portions of the first lower chip, which are not overlapped with the second lower chip, and to expose two adjacent edge portions of the second lower chip, which are not overlapped with the first lower chip.

7. The method of claim 1 , further comprising:
arranging a frame post in the frame and electrically connected with the redistribution post; and
arranging a wiring, which is electrically connected with the frame post, over the frame.

8. The method of claim 7 , further comprising:
arranging an external terminal on the wiring; and
arranging a logic chip on the second redistribution pattern.

9. The method of claim 1 , further comprising:
arranging an upper molding member on the first redistribution pattern to support the upper chip stack; and
arranging a lower molding member on the second redistribution pattern to support the lower chip stack.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kang Myungsam
• Ko Youngchan
• Park Yongjin

Classifications

• H10W90/20

  Configurations of stacked chips · CPC title

• H10W72/823

  Interconnections through encapsulations, e.g. pillars through molded resin on a lateral side a chip · CPC title

• H10W70/682

  comprising holes having chips therein · CPC title

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W90/291

  characterised by containers, encapsulations, or other housings for the stacked chips · CPC title