Multi-stack package-on-package structures

Patent metadata

Field	Value
Publication number	US-9806059-B1
Application number	US-201615153368-A
Country	US
Kind code	B1
Filing date	May 12, 2016
Priority date	May 12, 2016
Publication date	Oct 31, 2017
Grant date	Oct 31, 2017

Abstract

Multi-stack package-on-package structures are disclosed. In a method, a first stacked semiconductor device is formed on a first carrier wafer. The first stacked semiconductor device is singulated. The first stacked semiconductor device is adhered to a second carrier wafer. A second semiconductor device is attached on the first stacked semiconductor device. The second semiconductor device and the first stacked semiconductor device are encapsulated. Electrical connections are formed on and electrically coupled to the first stacked semiconductor device and the second semiconductor device.

First claim

What is claimed is:

1. A method comprising:
forming a first stacked semiconductor device on a first carrier wafer;
singulating the first stacked semiconductor device;
adhering the first stacked semiconductor device to a second carrier wafer;
attaching a second semiconductor device on the first stacked semiconductor device;
encapsulating the second semiconductor device and the first stacked semiconductor device;
singulating the first stacked semiconductor device and the second semiconductor device from the second carrier wafer; and
forming electrical connections on and electrically coupled to the first stacked semiconductor device and the second semiconductor device.

2. The method of claim 1 , wherein the second semiconductor device is a second stacked semiconductor device.

3. The method of claim 2 , wherein the first stacked semiconductor device comprises a plurality of memory dies, and wherein the second stacked semiconductor device comprises a plurality of memory dies.

4. The method of claim 1 , wherein the second semiconductor device is an integrated circuit die.

5. The method of claim 4 , wherein the first stacked semiconductor device comprises a plurality of memory dies, and wherein the second semiconductor device is a processor die.

6. The method of claim 1 , wherein no solder is formed in the first stacked semiconductor device during the forming the first stacked semiconductor device.

7. The method of claim 1 , wherein singulating the first stacked semiconductor device and the second semiconductor device from the second carrier wafer comprises:
removing the first stacked semiconductor device from the first carrier wafer; and
cutting along scribe lines of the first stacked semiconductor device.

8. The method of claim 7 , wherein the first carrier wafer is a glass wafer, and wherein the second carrier wafer is a glass wafer.

9. The method of claim 7 , wherein the first carrier wafer and the second carrier wafer are the same wafer.

10. The method of claim 1 , wherein singulating the first stacked semiconductor device comprises:
thinning the first carrier wafer; and
cutting along scribe lines of the first stacked semiconductor device and the first carrier wafer.

11. The method of claim 10 , wherein the first carrier wafer is a glass wafer, and wherein the second carrier wafer is a semiconductor substrate.

12. The method of claim 1 , wherein forming the first stacked semiconductor device comprises:
encapsulating a first layer of dies on the first carrier wafer;
forming conductive vias contacting external connectors of each of the first layer of dies;
providing a second layer of dies on the first layer of dies, the second layer of dies surrounded by the conductive vias; and
encapsulating the conductive vias and the second layer of dies.

13. A method comprising:
adhering a first plurality of dies to a device region on a first substrate;
forming a first plurality of through vias in electrical connection with the first plurality of dies;
attaching a second plurality of dies on the first plurality of dies, the second plurality of dies surrounded by the first plurality of through vias;
singulating the device region to form a stacked device;
adhering the stacked device to a second substrate;
providing a third die on the stacked device;
depositing an encapsulant on the stacked device and the third die; and
forming a redistribution layer over the encapsulant, the redistribution layer electrically coupled to the first plurality of dies, the second plurality of dies, and the third die.

14. The method of claim 13 , further comprising:
forming a second plurality of through vias in electrical connection with the first plurality of dies and the second plurality of dies.

15. The method of claim 14 , further comprising:
forming a first dielectric layer between the first plurality of dies and the second plurality of dies, wherein the first plurality of through vias extend through the first dielectric layer; and
forming a second dielectric layer between the second plurality of dies and the third die, wherein the second plurality of through vias extend through the second dielectric layer.

16. The method of claim 15 , wherein the first dielectric layer and the second dielectric layer are, respectively, layers in a first redistribution layer and a second redistribution layer.

17. A method comprising:
forming a first stacked semiconductor device comprising:
placing first integrated circuit dies over a first carrier wafer, each first integrated circuit die of the first integrated circuit dies having a dielectric layer over the first integrated circuit die and facing away from the first carrier wafer;
thinning the first carrier wafer; and
cutting along scribe lines of the first carrier wafer;

forming a second stacked semiconductor device comprising:
adhering the first stacked semiconductor device to a second carrier wafer;
attaching a second integrated circuit die on the first stacked semiconductor device; and
encapsulating the first stacked semiconductor device and the second integrated circuit die; and

forming electrical connections on and electrically coupled to the first integrated circuit dies and the second integrated circuit die.

18. The method of claim 17 , wherein the forming the first stacked semiconductor device further comprises:
forming respective encapsulant layers between the respective dielectric layers and surrounding each of the first integrated circuit dies.

19. The method of claim 17 , wherein the first stacked semiconductor device has a different fan-out ratio than the second stacked semiconductor device.

20. The method of claim 17 , wherein no solder is formed between each of the first integrated circuit dies during the forming the first stacked semiconductor device.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lee Chi-Jung
• Chen Hsien-Wei
• Su An-Jhih
• Chen Wei-Yu
• Yang Tien-Chung
• Huang Li-Hsien

Classifications

• H10P72/7416

  used during dicing or grinding · CPC title

• H10P72/74

  using temporarily an auxiliary support · CPC title

• H10P54/00

  Cutting or separating of wafers, substrates or parts of devices · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title