Contact resistance reduced P-MOS transistors employing Ge-rich contact layer

Patent metadata

Field	Value
Publication number	US-10535735-B2
Application number	US-201213539200-A
Country	US
Kind code	B2
Filing date	Jun 29, 2012
Priority date	Jun 29, 2012
Publication date	Jan 14, 2020
Grant date	Jan 14, 2020

Abstract

Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. The techniques can be implemented, for example, using a standard contact stack such as a series of metals on, for example, silicon or silicon germanium (SiGe) source/drain regions. In accordance with one example such embodiment, an intermediate boron-doped germanium-tin alloy layer is provided between the source/drain and contact metals to significantly reduce contact resistance. Numerous transistor configurations and suitable fabrication processes will be apparent in light of this disclosure, including both planar and non-planar transistor structures (e.g., FinFETs and nanowire transistors). The techniques are particularly well-suited for implementing p-type devices, but can be used for n-type devices if so desired.

First claim

What is claimed is:

1. A transistor device, comprising:
a semiconductor body above a top surface of a substrate;
a gate defining a channel region within the semiconductor body;
a pair of source/drain regions on opposite sides of the channel region; and
a Ge—Sn alloy layer comprising germanium, tin and boron on at least one of the source/drain regions, wherein a portion of the Ge—Sn alloy layer is above the at least one of the source/drain regions;
and a contact metal layer on the Ge—Sn alloy layer, the Ge—Sn alloy layer comprising a first interface region that is in direct contact with the at least one of the source/drain regions and a second interface region that is in direct contact with the contact metal layer, wherein the concentration of boron is graded in a direction normal to the top surface of the substrate within the portion of the Ge—Sn alloy layer and outside of the gate from a base level concentration of less than 1E19 cm −3 at the first interface to a concentration greater than 1E19 cm −3 , the concentration of Ge is greater than 70 atomic %, and the concentration of tin gradually increases from a base level in the first interface region to a predetermined level in the second interface region to reduce a contact resistance between the at least one of the source/drain regions and the contact metal layer.

2. The transistor device of claim 1 , wherein the base level of the tin concentration is 1 atomic % and the predetermined level of the tin concentration is 15 atomic %.

3. The transistor device of claim 1 , wherein the base level of the tin concentration is 3 atomic % and the predetermined level of the tin concentration is 10 atomic %.

4. The transistor device of claim 1 , wherein the semiconductor body comprises a fin; and wherein the Ge—Sn alloy layer is deposited on at least two sides of the fin.

5. The transistor device of claim 1 , wherein the Ge—Sn alloy layer is polycrystalline.

6. The transistor device of claim 1 , wherein the contact metal comprises a metal germanide.

7. The transistor device of claim 1 , wherein the Ge—Sn alloy layer comprises less than 10% Si.

8. The transistor device of claim 1 , wherein the Ge—Sn alloy layer comprises less than 5% Si.

9. The transistor device of claim 1 , further comprising a graded buffer layer having a graded Ge concentration between the at least one source/drain region and the Ge—Sn alloy layer.

10. The transistor device of claim 9 , wherein the graded Ge concentration is from a base level concentration compatible with the source/drain region to a high concentration in excess of 90 atomic %.

11. The transistor device of claim 1 , wherein the predetermined level of the tin concentration is 30 atomic %, and the base level of the tin concentration is less than 30 atomic %.

12. The transistor device of claim 9 , wherein the graded buffer layer has a boron concentration that increases from a base level concentration compatible with the source and drain regions to a high concentration in excess of 1E19 cm′.

13. The transistor device of claim 1 , wherein the semiconductor body has a silicon concentration in excess of 10 atomic %.

14. A transistor device, comprising:
a gate defining a channel region within a silicon body, the silicon body above a top surface of a substrate;
a pair of silicon germanium source/drain regions on opposite sides of the channel region;
a Ge—Sn alloy layer comprising germanium, tin and boron on at least one of the source/drain regions, wherein a portion of the Ge—Sn alloy layer is above the at least one of the source/drain regions; and
a contact metal layer on the Ge—Sn alloy layer, the Ge—Sn alloy layer comprising a first interface region that is in direct contact with the at least one of the source/drain regions and a second interface region that is in direct contact with the contact metal layer, wherein the concentration of boron is graded in a direction normal to the top surface of the substrate within the portion of the Ge—Sn alloy layer and outside of the gate from a base level concentration of less than 1E19 cm −3 at the first interface to a concentration greater than 1E19 cm −3 , the concentration of germanium is greater than 75 atomic %, the concentration of tin gradually increases from a base level in the first interface region to 15 atomic % in the second interface region to reduce a contact resistance between the at least one of the source/drain regions and the contact metal layer.

15. The transistor device of claim 14 , wherein the contact metal layer comprises a metal selected from the group consisting of Ti, Pt, Ni, and Co.

16. The transistor device of claim 15 , wherein the contact metal layer further comprises a metal silicide.

17. The transistor device of claim 15 , wherein the contact metal layer further comprises a metal germanide.

18. The transistor device of claim 14 , further comprising a graded buffer layer between the at least one of the source/drain regions and the Ge—Sn alloy layer.

19. The transistor device of claim 14 , wherein the Ge—Sn alloy layer comprises less than 5% Si.

20. A method, comprising:
forming a gate stack defining a channel region of a semiconductor device and a pair of source/drain regions on opposite sides of the channel region, the channel region above a top surface of a substrate;
blanket depositing a dielectric material over the semiconductor device;
etching a trench in the dielectric material to expose at least a portion of at least one of the source/drain regions; and
forming a Ge—Sn alloy layer comprising germanium, tin and boron within the trench on at least the portion of the at least one of the source/drain regions, wherein a portion of the Ge—Sn alloy layer is above the at least one of the source/drain regions,
depositing a contact metal layer on the Ge—Sn alloy layer, the Ge—Sn alloy layer comprising a first interface region that is in direct contact with the at least one of the source/drain regions and a second interface region that is in direct contact with the contact metal layer, wherein the concentration of boron is graded in a direction normal to the top surface of the substrate within the portion of the Ge—Sn alloy layer and outside of the gate from a base level concentration of less than 1E19 cm −3 at the first interface to a concentration greater than 1E19 cm −3 , the concentration of germanium is greater than 70 atomic %, and the concentration of tin gradually increases from a base level in the first interface region to a predetermined level in the second interface region to reduce a contact resistance between the at least one of the source/drain regions and the contact metal layer.

21. The method of claim 20 , further comprising depositing a contact plug over the contact metal layer.

22. The method of claim 20 , further comprising forming a graded buffer layer on the at least one of the source/drain regions.

23. The method of claim 20 , wherein the Ge—Sn alloy layer is formed by at least one of a selective deposition, or a molecular beam epitaxy.

24. The method of claim 20 , wherein the Ge—Sn alloy layer is formed by a chemical vapor deposition.

Assignees

• Glass Glenn A
• Murthy Anand S
• Intel Corp

Inventors

• Glass Glenn A
• Murthy Anand S

Classifications

• B82Y10/00

  Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic · CPC title

• H01L29/1033 Primary

  Electricity · mapped topic

• H10D62/834

  further characterised by the dopants · CPC title

• H10D62/121

  oriented parallel to substrates · CPC title

• H10D30/797

  being in source or drain regions, e.g. SiGe source or drain · CPC title