CMOS architecture with thermally stable silicide gate workfunction metal
US-12575184-B2 · Mar 10, 2026 · US
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Acton Orb patents
Acton Orb is listed as an inventor on 20 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Acton Orb |
| Total patents | 20 |
| First publication | Jan 2, 2020 |
| Latest publication | Mar 10, 2026 |
Notable patents
Publications ranked by popularity score, then publication date.
Selective templated aligned at recess dual metal gate patterning
US-2026006891-A1 · Jan 1, 2026 · US
Selective templated aligned at recess dual metal gate patterning
US-2026006892-A1 · Jan 1, 2026 · US
Contact over active gate structures with gate recess for gate insulating cap layers for advanced integrated circuit structure fabrication
US-2025391774-A1 · Dec 25, 2025 · US
Dipole threshold voltage tuning for high voltage transistor stacks
US-12471354-B2 · Nov 11, 2025 · US
Gate-all-around integrated circuit structures having uniform threshold voltages and tight gate endcap tolerances
US-12310060-B2 · May 20, 2025 · US
Multi-threshold scheme using dual dipole patterning in complementary transistor dielectrics
US-2025113598-A1 · Apr 3, 2025 · US
Fabrication of gate-all-around integrated circuit structures having multi-layer molybdenum metal gate stack
US-2024332394-A1 · Oct 3, 2024 · US
Metal gate fabrication for nanoribbon-based transistors
US-2024290788-A1 · Aug 29, 2024 · US
Fabrication of gate-all-around integrated circuit structures having molybdenum nitride metal gates and gate dielectrics with a dipole layer
US-12051698-B2 · Jul 30, 2024 · US
Recent patents
Latest publications not already listed above.
Leave-behind protective layer having secondary purpose
US-11996408-B2 · May 28, 2024 · US
Fabrication of gate-all-around integrated circuit structures having common metal gates and having gate dielectrics with an opposite polarity dipole layer
US-2023420531-A1 · Dec 28, 2023 · US
Gate-all-around integrated circuit structures having uniform threshold voltages and tight gate endcap tolerances
US-2022416039-A1 · Dec 29, 2022 · US
Silicide structure of an integrated transistor device and method of providing same
US-11476334-B2 · Oct 18, 2022 · US
Leave-behind protective layer having secondary purpose
US-2022246608-A1 · Aug 4, 2022 · US
Dipole threshold voltage tuning for high voltage transistor stacks
US-2022199472-A1 · Jun 23, 2022 · US
Leave-behind protective layer having secondary purpose
US-11348916-B2 · May 31, 2022 · US
Fabrication of gate-all-around integrated circuit structures having molybdenum nitride metal gates and gate dielectrics with a dipole layer
US-2022093597-A1 · Mar 24, 2022 · US
Silicide structure of an integrated transistor device and method of providing same
US-2020343343-A1 · Oct 29, 2020 · US
Leave-behind protective layer having secondary purpose
US-2020006330-A1 · Jan 2, 2020 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Intel Corp | 20 |
| Lilak Aaron D | 1 |
| Acton Orb | 1 |
| Huang Cheng Ying | 1 |
| Dewey Gilbert | 1 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| H10D84/038 | 17 |
| H10D64/667 | 15 |
| H10D84/0177 | 14 |
| H10D30/6757 | 13 |
| H10D30/6735 | 13 |