Semiconductor devices including supporter

Patent metadata

Field	Value
Publication number	US-11996352-B2
Application number	US-202217888727-A
Country	US
Kind code	B2
Filing date	Aug 16, 2022
Priority date	Jan 20, 2020
Publication date	May 28, 2024
Grant date	May 28, 2024

Abstract

A semiconductor device includes a substrate including a cell region and a connection region. The connection region includes a plurality of pad regions and a through electrode region. A horizontal conductive layer is on the substrate. A supporter is on the horizontal conductive layer. The supporter includes a first portion in the cell region, a second portion in the plurality of pad regions, and a third portion in the through electrode region. A connection conductive layer is between the first portion and the horizontal conductive layer. A connection mold layer is between the third portion and the horizontal conductive layer. A first buried insulation layer passing through the third portion, the connection mold layer, and the horizontal conductive layer is provided. A stacked structure is on the substrate. A through electrode passing through the first buried insulation layer is provided.

First claim

What is claimed is:

1. A semiconductor device comprising:
a substrate including a first region, a second region, and a third region;
a horizontal conductive layer on the substrate;
a supporter on the horizontal conductive layer, the supporter including a first portion in the first region and a second portion in the second region, and a third portion in the third region;
a connection conductive layer between the first portion of the supporter and the horizontal conductive layer;
a connection mold layer between the third portion of the supporter and the horizontal conductive layer; and
a cell channel structure in the first region to pass through a stacked structure where a plurality of insulation layers and a plurality of wiring layers are alternately stacked and the supporter and extend to an inner portion of the horizontal conductive layer;
wherein a level of an upper surface of the supporter in the second region is lower than a level of an upper surface of the supporter in the third region.

2. The semiconductor device of claim 1 , wherein the level of an upper surface of the supporter in the second region is lower than a level of an upper surface of the supporter in the first region.

3. The semiconductor device of claim 1 , wherein the upper surfaces of the first portion and the third portion are substantially coplanar.

4. The semiconductor device of claim 1 , wherein a distance between an uppermost end of the second portion and a top surface of the substrate is shorter than a distance between an uppermost end of the first portion and the top surface of the substrate.

5. The semiconductor device of claim 1 , wherein a bottom surface of the second portion contacts the horizontal conductive layer.

6. The semiconductor device of claim 1 , further comprising:
a first buried insulation layer in the third region to pass through supporter, the connection mold layer, and the horizontal conductive layer, and
a through electrode in the third region to pass through the first buried insulation layer.

7. The semiconductor device of claim 6 , wherein upper surfaces of the first portion, the third portion, and the first buried insulation layer are substantially coplanar.

8. The semiconductor device of claim 1 , wherein
the stacked structure extends to the second region, and
a minimum interval between a corresponding wiring layer of the plurality of wiring layers and the second portion is greater than a minimum interval between the corresponding wiring layer and the first portion.

9. The semiconductor device of claim 1 , wherein
the stacked structure extends to the second region and the third region,
each of the plurality of wiring layers comprises an electrode layer and a mold layer connecting with a side surface of the electrode layer, and
a minimum interval between the electrode layer and the third portion is greater than a minimum interval between the electrode layer and the first portion.

10. The semiconductor device of claim 9 , wherein
the mold layer is disposed on the third region, and
the electrode layer is disposed on the first and the second regions.

11. The semiconductor device of claim 1 , wherein
the second region is a plurality of regions extending from at least one side of the first region, and
the third region is between the plurality of regions.

12. The semiconductor device of claim 1 , further including:
a plurality of gate contact plugs connected to the plurality of wiring layers in the second region;
a plurality of transistors between the substrate and horizontal conductive layer, and
a through electrode passing through the stacked structure and electrically connected to the plurality of transistors in third region.

13. A semiconductor device comprising:
a substrate including a first region, a second region, and a third region;
a horizontal conductive layer on the substrate;
a supporter on the horizontal conductive layer, the supporter including a first portion in the first region, a second portion in the second region, and a third portion in the third region;
a connection conductive layer between the first portion of the supporter and the horizontal conductive layer;
a connection mold layer between the third portion of the supporter and the horizontal conductive layer;
a stacked structure where a plurality of insulation layers and a plurality of wiring layers are alternately stacked on the supporter, and
a cell channel structure in the first region to pass through the stacked structure and the first portion and extend to an inner portion of the horizontal conductive layer,
wherein each of the plurality of wiring layers comprises an electrode layer in the first and second regions and a mold layer in the third region,
wherein a level of an upper surface of the supporter in the second region is lower than a level of an upper surface of the supporter in the third region.

14. The semiconductor device of claim 13 , further comprising:
a first buried insulation layer in the third region to pass through the third portion, the connection mold layer, and the horizontal conductive layer;
a second buried insulation layer in the second region to cover the second portion, and
a through electrode in the third region to pass through the stacked structure and the first buried insulation layer.

15. The semiconductor device of claim 14 , wherein
the mold layer is aligned on the first buried insulation layer, and
the mold layer has a width which is greater than a width of the first buried insulation layer.

16. The semiconductor device of claim 14 , wherein
the third portion and connection mold layer surround side surfaces of the first buried insulation layer.

17. The semiconductor device of claim 13 , wherein
the mold layer overlaps the third portion, and
the mold layer has a width which is greater than a width of the third portion.

18. A semiconductor device comprising:
a substrate including a first region, a second regions extending from at least one side of the first region, and a third region between second regions, the first to third regions connected with each other;
a horizontal conductive layer on the substrate;
a supporter on the horizontal conductive layer;
a connection conductive layer between the supporter and the horizontal conductive layer in the first region;
a first buried insulation layer passing through the supporter and the horizontal conductive layer in the third region;
a cell channel structure passing through a stacked structure where a plurality of insulation layers and a plurality of wiring layers are alternately stacked and the supporter in the first region, and extend to an inner portion of the horizontal conductive layer; and
a through electrode passing through the first buried insulation layer in the third region,
wherein a level of an upper surface of the supporter in the second regions is lower than a level of an upper surface of the supporter in the first region and a level of an upper surface of the supporter in the third region.

19. The semiconductor device of claim 18 , the level of the upper surface of the supporter in the first region is substantially the same as the level of the upper surface of the supporter in the third region.

20. The semiconductor device of claim 18 , the level of the upper surface of the supporter in the second regions is lower than a level of an upper surface of the first buried insulation layer.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Yang Woosung
• Kim Jiyoung
• Kim Jiwon

Classifications

• H10W20/20 Primary

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10D30/69

  IGFETs having charge trapping gate insulators, e.g. MNOS transistors · CPC title

• H10D30/0413

  of FETs having charge-trapping gate insulators, e.g. MNOS transistors · CPC title

• H01L23/481 Primary

  Electricity · mapped topic

• H10B43/27

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title