Semiconductor device and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-10553602-B2
Application number	US-201816217876-A
Country	US
Kind code	B2
Filing date	Dec 12, 2018
Priority date	Nov 8, 2016
Publication date	Feb 4, 2020
Grant date	Feb 4, 2020

Abstract

A semiconductor device includes gate stacked structures surrounding channel layers, a common source line filling a separation area between the gate stacked structures adjacent to each other and having an upper surface including first concave portions, and a support insulating layer filling the first concave portions and having sidewalls facing portions of the channel layers.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor device, the method comprising:
forming a stacked structure including first material layers and second material layers stacked alternately with each other;
forming first slits passing through the stacked structure and spaced apart from each other in a first direction;
filling a lower portion of each of the first slits with a third material layer;
filling an upper portion of each of the first slits with a fourth material layer;
forming a second slit passing through the first material layers and the second material layers and neighboring the first slits in the first direction when the stacked structure is supported by the third material layer and the fourth material layer; and
removing the third material layer through the second slit when the first material layers are supported by the fourth material layer.

2. The method of claim 1 , further comprising, when the second material layers include a sacrificial material having an etch rate different from the first material layers:
removing the second material layers through the second slit when the first material layers are supported by the fourth material layer; and
filling regions from which the second material layers are removed with gate conductive materials.

3. The method of claim 1 , wherein the stacked structure is divided into a plurality of gate stacked structures by the first slits and the second slit when the second material layers include gate conductive materials.

4. The method of claim 1 , further comprising, before the third material layer and the fourth material layer are formed:
forming a protective layer including a material having an etch rate different from the third material layer on sidewalls of each of the first slits.

5. The method of claim 1 , wherein the fourth material layer has an etch rate different from the third material layer.

6. The method of claim 1 , further comprising:
forming a sidewall insulating layer on a surface of the second slit and a surface from which the third material layer is removed;
partially etching the sidewall insulating layer to open a bottom surface of the second slit; and
forming a common source line on the sidewall insulating layer to fill the second slit and a region from which the third material layer is removed.

7. The method of claim 6 , wherein the common source line is extended to contact a source layer arranged below the stacked structure.

8. The method of claim 7 , wherein the forming of the source layer comprises:
forming a source stacked structure including a base source layer and a sacrificial source layer arranged over the base source layer;
forming first source holes and second source holes passing through the sacrificial source layer and extending into the base source layer;
forming first sacrificial pillars filling the first source holes and second sacrificial pillars filling the second source holes;
opening a source region by removing the sacrificial source layer through the second slit; and
forming a contact source layer contacting the base source layer in the source region through the second slit.

9. The method of claim 8 , wherein the first sacrificial pillars and the second sacrificial pillars are formed before the stacked structure is formed,
the method further comprising:
forming through holes passing through the stacked structure to expose the first sacrificial pillars;
removing the first sacrificial pillars through the through holes to open channel holes coupled to the through holes and the first source holes;
forming a multilayer memory layer on a surface of each of the channel holes; and
forming a channel layer on the multilayer memory layer.

10. The method of claim 9 , further comprising, before the forming of the contact source layer:
partially removing the multilayer memory layer through the second slit to expose sidewalk of the channel layer by the source region,
wherein the contact source layer contacts the sidewalks of the channel layer exposed by the source region.

11. The method of claim 8 , further comprising, before the third material layer and the fourth material layer are formed:
removing the second sacrificial pillars through the first slit to open the second source holes; and
filling the second source holes with insulating plugs.

12. The method of claim 8 , wherein the second sacrificial pillars overlap with the first slits.

Assignees

• Sk Hynix Inc

Inventors

• Lee Ki Hong

Classifications

• H01L27/11565

  Electricity · mapped topic

• H01L27/11568 Primary

  Electricity · mapped topic

• H01L27/11582

  Electricity · mapped topic

• H01L27/1157

  Electricity · mapped topic

• H10B41/50

  characterised by the boundary region between the core region and the peripheral circuit region · CPC title