Methods and heat distribution devices for thermal management of chip assemblies

US11990386B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11990386-B2
Application numberUS-202117333570-A
CountryUS
Kind codeB2
Filing dateMay 28, 2021
Priority dateMay 29, 2020
Publication dateMay 21, 2024
Grant dateMay 21, 2024

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A method of manufacturing a chip assembly comprises joining an in-process unit to a printed circuit board; reflowing a bonding material disposed between and electrically connecting the in-process unit with the printed circuit board, the bonding material having a first reflow temperature; and then joining a heat distribution device to the plurality of semiconductor chips using a thermal interface material (“TIM”) having a second reflow temperature that is lower than the first reflow temperature. The in-process unit further comprises a substrate having an active surface, a passive surface, and contacts exposed at the active surface; an interposer electrically connected to the substrate; a plurality of semiconductor chips overlying the substrate and electrically connected to the substrate through the interposer, and a stiffener overlying the substrate and having an aperture extending therethrough, the plurality of semiconductor chips being positioned within the aperture.

First claim

Opening claim text (preview).

The invention claimed is: 1. A method of manufacturing a chip assembly comprising: joining an in-process unit to a printed circuit board, the in-process unit comprising: a substrate having an active surface, a passive surface, and contacts exposed at the active surface; an interposer electrically connected to the substrate; a plurality of semiconductor chips overlying the substrate and electrically connected to the substrate through the interposer; and a stiffener overlying the substrate and having an aperture extending therethrough, the plurality of semiconductor chips being positioned within the aperture; reflowing a bonding material disposed between and electrically connecting the in-process unit with the printed circuit board, the bonding material having a first reflow temperature; and then joining a heat distribution device to the plurality of semiconductor chips using a thermal interface material (“TIM”) having a second reflow temperature that is lower than the first reflow temperature, wherein the heat distribution device includes a base, a plurality of thermally conductive fins extending from at least a portion of the base, and a lid, and wherein the base is comprised of a material having a thermal conductivity greater than 394 W/m 2 , and wherein at least one of the lid and the plurality of thermally conductive fins is comprised of a material having a thermal conductivity of 394 W/m 2 or less. 2. The method of claim 1 , wherein the heat distribution device comprises a cold plate having the base and the lid coupled to the base, the method further comprising joining the base of the cold plate to rear surfaces of the plurality of semiconductor chips prior to coupling the lid to the base. 3. The method of claim 2 , further comprising joining the base of the cold plate to a top surface of the stiffener. 4. The method of claim 1 , wherein the heat distribution device comprises a cold plate having a base and a lid coupled to the base, the method further comprising joining the base and the lid together, and then joining the base to rear surfaces of the plurality of semiconductor chips. 5. The method of claim 1 , wherein prior to joining the heat distribution device to rear surfaces of the plurality of semiconductor chips, the TIM is provided on one of the rear surfaces of the semiconductor chips or a bottom surface of the heat distribution device. 6. A method of manufacturing a chip assembly comprising: joining an in-process unit to a printed circuit board, the in-process unit comprising: a substrate having an active surface, a passive surface, and contacts exposed at the active surface; an interposer electrically connected to the substrate; a plurality of semiconductor chips overlying the substrate and electrically connected to the substrate through the interposer; and a stiffener overlying the substrate and having an aperture extending therethrough, the plurality of semiconductor chips being positioned within the aperture; reflowing a bonding material disposed between and electrically connecting the in-process unit with the printed circuit board, the bonding material having a first reflow temperature; and then joining a heat distribution device to the plurality of semiconductor chips using a thermal interface material (“TIM”) having a second reflow temperature that is lower than the first reflow temperature, wherein the heat distribution device further comprises a plurality of thermally conductive fins, wherein a first fin length of at least some of the plurality of thermally conductive fins is greater than a second fin length of remaining fins of the plurality of thermally conductive fins, wherein a first height of at least one of the plurality of semiconductor chips is less than a second height of others of the plurality of semiconductor chips, and wherein the method further comprises positioning the at least some of the plurality of thermally conductive fins having a first fin length to overlie the at least one of the plurality of semiconductor chips having the first height. 7. The method of claim 1 , wherein during the reflowing a compression device applies pressure to the heat distribution device. 8. The method of claim 7 , wherein the compression device is a weight configured to overlie the heat distribution device during manufacturing of the chip assembly, the method further comprising applying the weight to a top surface of the heat distribution device. 9. The method of claim 7 , wherein the compression device includes a rigid plate and springs at opposed ends of the rigid plate, the method further comprising positioning the rigid plate over a rear surface of the heat distribution device and securing the rigid plate to the printed circuit board. 10. The method of claim 2 , wherein the heat distribution device further includes an inlet and an outlet, and wherein the method further includes providing fluid connections to connect the inlet and outlet to a fluid source so as to enable introduction and ejection of fluid into and out of the heat distribution device. 11. A method of manufacturing a chip assembly comprising: joining an in-process unit to a printed circuit board, the in-process unit comprising: a substrate having an active surface, a passive surface, and contacts exposed at the active surface; an interposer electrically connected to the substrate; a plurality of semiconductor chips overlying the substrate and electrically connected to the substrate through the interposer; and a stiffener overlying the substrate and having an aperture extending therethrough, the plurality of semiconductor chips being positioned within the aperture; reflowing a bonding material disposed between and electrically connecting the in-process unit with the printed circuit board, the bonding material having a first reflow temperature; and then joining a heat distribution device to the plurality of semiconductor chips using a thermal interface material (“TIM”) having a second reflow temperature that is lower than the first reflow temperature, wherein providing an in-process unit further comprises providing a plurality of in-process units, and wherein providing a heat distribution device further comprises providing a plurality of heat distribution devices, the method further comprising: bonding the plurality of in-process units to the printed circuit board by reflowing a bonding material that joins contacts of each of the substrates within the plurality of in-process units with contacts of the printed circuit board; joining each of the plurality of heat distribution devices to a corresponding one of the plurality of semiconductor chips of the plurality of in-process units by reflowing a high thermally conductive thermal interface material (“TIM”), each of the plurality of heat distribution devices comprising a plurality of thermally conductive fins, an inlet, and an outlet; and joining the inlets and outlets of the plurality of the heat distribution devices to one another so that the inlet and outlet of one of the plurality of heat distribution devices of the plurality of in-process units are in fluid connection with the inlet and outlet of another heat distribution device of the plurality of heat distribution devices. 12. The method of claim 6 , wherein the TIM is solder. 13. The method of claim 1 , wherein the TIM is solder. 14. The method of claim 6 , wherein the heat distribution device comprises a cold plate having a base and a lid coupled to the base, the method further comprising joining the base of the cold plate to rear surfaces of the plurality of semiconductor chips prior to coupling the lid to the base

Assignees

Inventors

Classifications

  • Bump connectors and die-attach connectors · CPC title

  • between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

  • Package configurations · CPC title

  • characterised by changes in properties of the die-attach connectors during connecting · CPC title

  • Die-attach connectors · CPC title

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What does patent US11990386B2 cover?
A method of manufacturing a chip assembly comprises joining an in-process unit to a printed circuit board; reflowing a bonding material disposed between and electrically connecting the in-process unit with the printed circuit board, the bonding material having a first reflow temperature; and then joining a heat distribution device to the plurality of semiconductor chips using a thermal interfac…
Who is the assignee on this patent?
Google Llc
What technology area does this patent fall under?
Primary CPC classification H10W40/254. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue May 21 2024 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 12 related publications on this page (citations in our corpus or others sharing the same primary CPC).