Semiconductor packaging structure and process

Patent metadata

Field	Value
Publication number	US-9735043-B2
Application number	US-201314137478-A
Country	US
Kind code	B2
Filing date	Dec 20, 2013
Priority date	Dec 20, 2013
Publication date	Aug 15, 2017
Grant date	Aug 15, 2017

Abstract

A method and structure for packaging a semiconductor device are provided. In an embodiment a first substrate is bonded to a second substrate, which is bonded to a third substrate. A thermal interface material is placed on the second substrate prior to application of an underfill material. A ring can be placed on the thermal interface material, and an underfill material is dispensed between the second substrate and the third substrate. By placing the thermal interface material and ring prior to the underfill material, the underfill material cannot interfere with the interface between the thermal interface material and the second substrate, and the thermal interface material and ring can act as a physical barrier to the underfill material, thereby preventing overflow.

First claim

What is claimed is:

1. A method for manufacturing a semiconductor device, the method comprising:
bonding a first substrate to a first side of a second substrate;
placing a first thermal interface material on the second substrate to a thickness of between about 5 μm and about 500 μm, wherein the placing the first thermal interface material places the first thermal interface material on the first side; and
dispensing underfill material between the first substrate and the second substrate, the dispensing occurring after the placing the first thermal interface material on the second substrate, wherein during the dispensing the underfill material the first thermal interface material is part of a structure with a first exposed surface facing away from the first side, the first exposed surface being located a first distance away from the first side and wherein the first substrate has a second surface facing away from the first side, the second surface being located a second distance away from the first side, the second distance being greater than the first distance, wherein after the dispensing the underfill material the underfill material has a third surface facing away from the second substrate that is in contact with both the first thermal interface material and a sidewall of the first substrate perpendicular to the second substrate, the third surface being closer to second substrate than the second surface.

2. The method of claim 1 , further comprising placing a ring onto the first thermal interface material prior to the dispensing the underfill material.

3. The method of claim 2 , further comprising curing the first thermal interface material prior to the dispensing the underfill material.

4. The method of claim 2 , further comprising dispensing a second thermal interface material onto the ring after the dispensing the underfill material.

5. The method of claim 4 , further comprising attaching a lid, wherein the lid is in physical connection with the second thermal interface material.

6. The method of claim 1 , further comprising attaching a lid, wherein the lid is in physical connection with the first thermal interface material.

7. The method of claim 1 , further comprising bonding the second substrate to a third substrate.

8. A method of manufacturing a semiconductor device, the method comprising:
dispensing a first thermal interface material onto a first side of a first substrate, wherein a second substrate is bonded to the first side of the first substrate prior to the dispensing the first thermal interface material;
placing a ring onto the first thermal interface material, wherein the second substrate extends further from the first substrate than the ring;
applying an underfill material between the first substrate and the second substrate, wherein after the applying the underfill material the underfill material extends in a first direction from a first point to physically contact the first thermal interface material, the first point being between the first substrate and the second substrate, and wherein the underfill material extends in a second direction from the first point only partially towards the first thermal interface material; and
attaching a lid over the first substrate and the second substrate, the lid being in thermal connection with the ring.

9. The method of claim 8 , further comprising curing the first thermal interface material after the placing the ring onto the first thermal interface material.

10. The method of claim 8 , further comprising bonding the first substrate to a third substrate.

11. The method of claim 8 , further comprising dispensing a second thermal interface material onto the ring after the applying the underfill material.

12. The method of claim 11 , further comprising dispensing a third thermal interface material onto the second substrate, wherein the attaching the lid over the first substrate and the second substrate further comprises placing the lid in contact with the third thermal interface material.

13. The method of claim 12 , wherein the lid has a first region with a first thickness, a second region with a second thickness different from the first thickness, and a third region with a third thickness different from the first thickness and the second thickness, wherein the first region is in contact with the third thermal interface material, the second region is in contact with the second thermal interface material, and the third region is in contact with an adhesive on a third substrate.

14. The method of claim 8 , wherein the lid has a constant thickness along its length.

15. A method of manufacturing a semiconductor device, the method comprising:
bonding a first substrate to a second substrate, wherein the first substrate comprises a first section that laterally extends beyond the second substrate;
bonding a third substrate to the second substrate, wherein the second substrate comprises a second section that laterally extends beyond the third substrate;
placing a first thermal interface material on the second substrate in the second section;
dispensing a first underfill material between the second substrate and the third substrate after the placing the first thermal interface material, wherein the first thermal interface material prevents the first underfill material from flowing in the first direction and wherein at an end of the dispensing the first underfill material the first underfill material contacts the first thermal interface material at a point that is located a first distance away from the first substrate, the first thermal interface material extending away from the first substrate a second distance greater than the first distance; and
placing a lid in thermal connection with the first thermal interface material, the third substrate, and the first section of the first substrate, wherein the lid has a first thickness over the first section of the first substrate, a second thickness different from the first thickness over the first thermal interface material, and a third thickness different from the first thickness and the second thickness over the third substrate.

16. The method of claim 15 , further comprising placing a second thermal interface material on the third substrate prior to the placing the lid.

17. The method of claim 15 , further comprising placing a ring over the first thermal interface material prior to the placing the lid.

18. The method of claim 17 , further comprising placing a third thermal interface material on the ring prior to the placing the lid, wherein the lid is in physical contact with the third thermal interface material.

19. The method of claim 15 , wherein the placing the lid further comprises placing a heat sink.

20. The method of claim 15 , further comprising curing the first thermal interface material after the placing the first thermal interface material.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Ho Kuan-Lin
• Chen Chin-Liang
• Lin Wei-Ting
• Liu Yu-Chih
• Lin Shih-Yen

Classifications

• H10W76/63

  characterised by their shape or disposition, e.g. between cap and walls of a container · CPC title

• H10W76/60

  Seals · CPC title

• H10W90/288

  characterised by arrangements for thermal management of the stacked chips · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W72/072

  of bump connectors · CPC title