Metal cut patterning and etching to minimize interlayer dielectric layer loss

Patent metadata

Field	Value
Publication number	US-11990342-B2
Application number	US-202117481516-A
Country	US
Kind code	B2
Filing date	Sep 22, 2021
Priority date	Dec 18, 2017
Publication date	May 21, 2024
Grant date	May 21, 2024

Abstract

The present disclosure relates to methods and apparatuses related to the deposition of a protective layer selective to an interlayer dielectric layer so that the protective layer is formed onto a top portion associated with the interlayer dielectric layer. In some embodiments, a method comprises: forming an interlayer dielectric layer on a substrate; covering a trench region with a metal liner, wherein the trench region is situated above the substrate and formed within the interlayer dielectric layer; and depositing a protective layer selective to the interlayer dielectric layer so that the protective layer is formed onto a top portion associated with the interlayer dielectric layer. In various embodiments, the depositing the protective layer comprises: repeatedly depositing the protective layer via a multi-deposition sequence; or depositing a self-assembled monolayer onto the top portion.

First claim

What is claimed is:

1. An apparatus, comprising:
an interlayer dielectric layer formed on a substrate;
a first protective layer that covers:
a top portion associated with the interlayer dielectric layer, and
a trench region formed within the interlayer dielectric layer situated above the substrate;

a metal liner coating the first protective layer covering the trench region; and
a second protective layer resistant to anisotropic metal etching and selective to the first protective layer so that the second protective layer is formed, due to selectivity of the second protective layer, on the first protective layer covering the top portion and is not formed, due to the selectivity of the second protective layer, on the metal liner, wherein the second protective layer maintains interlayer dielectric layer oxide loss below a threshold and prevents blockage of source-drain contact etching during the anisotropic metal etching, wherein the first protective layer comprises hafnium dioxide, and wherein the second protective layer is formed via selective deposition of a self-assembled monolayer comprising phosphonic acid terminated groups that bind to the hafnium dioxide.

2. The apparatus of claim 1 , wherein the first protective layer comprises a material having a dielectric constant greater than 3.9.

3. The apparatus of claim 1 , wherein the second protective layer is formed via a multi-deposition sequence.

4. The apparatus of claim 1 , wherein the second protective layer comprises an organic material.

5. The apparatus of claim 1 , wherein the second protective layer comprises a polymer.

6. An apparatus, comprising:
an interlayer dielectric layer formed on a substrate;
a first protective layer that includes a material comprising hafnium dioxide and that covers:
a top portion associated with the interlayer dielectric layer, and
a trench region formed within the interlayer dielectric layer situated above the substrate;

a metal liner coating the first protective layer covering the trench region;
a metallic filler occupying a volume bounded by the metal liner within the trench region; and
a second protective layer resistant to anisotropic metal etching and selective to the first protective layer so that the second protective layer coats, due to selectivity of the second protective layer, the first protective layer covering the top portion and does not coat, due to the selectivity of the second protective layer, the metal liner or the metallic filler, wherein the second protective layer is formed via selective deposition of a self-assembled monolayer comprising phosphonic acid terminated groups that bind to hafnium dioxide or to titanium dioxide.

7. The apparatus of claim 6 , wherein the material comprises a dielectric constant greater than 3.9.

8. The apparatus of claim 6 , wherein the second protective layer is formed via a multi-deposition sequence.

9. The apparatus of claim 6 , wherein the second protective layer comprises an organic material.

10. The apparatus of claim 6 , wherein the second protective layer comprises a polymer.

11. The apparatus of claim 6 , wherein the second protective layer comprises a self-assembled monolayer.

12. The apparatus of claim 6 , wherein the second protective layer comprises at least one member selected from a group consisting of silicon dioxide, silicon nitride, and hafnium dioxide.

13. An apparatus, comprising:
an interlayer dielectric layer positioned on a substrate and comprising a trench region;
a metal liner positioned within the trench region; and
a protective layer positioned adjacent to the interlayer dielectric layer, the protective layer being resistant to anisotropic metal etching and selective to a dielectric layer, the dielectric layer being positioned between the metal liner and the interlayer dielectric layer, and the dielectric layer being further positioned between the protective layer and the interlayer dielectric layer, wherein the dielectric layer comprises hafnium dioxide, wherein the protective layer is formed via selective deposition of a self-assembled monolayer comprising phosphonic acid terminated groups that bind to the hafnium dioxide, and wherein the protective layer prevents blockage of source-drain contact etching during the anisotropic metal etching.

14. The apparatus of claim 13 , wherein the protective layer is formed, due to selectivity of the protective layer, on the dielectric layer and is not formed, due to the selectivity of the protective layer, on the metal liner.

15. The apparatus of claim 14 , wherein the dielectric layer comprises a material having a dielectric constant greater than 3.9.

16. The apparatus of claim 15 , wherein the material comprises zirconium dioxide.

17. The apparatus of claim 13 , wherein the dielectric layer is positioned on a top portion of the interlayer dielectric layer.

Assignees

• IBM

Inventors

• Chung Kisup
• De Silva Ekmini Anuja
• Greene Andrew
• Kanakasabapathy Siva
• Seshadri Indira

Classifications

• H10D64/01332

  Making the insulator · CPC title

• H10D64/01354 Primary

  passivation or protection of the electrode, e.g. using re-oxidation · CPC title

• H10D84/0153

  using gate cut processes · CPC title

• H10D84/038 Primary

  using silicon technology, e.g. SiGe · CPC title

• H10D64/691

  comprising metallic compounds, e.g. metal oxides or metal silicates  (insulators comprising nitrogen H10D64/693) · CPC title