Critical dimension shrink through selective metal growth on metal hardmask sidewalls

Patent metadata

Field	Value
Publication number	US-9595473-B2
Application number	US-201514727132-A
Country	US
Kind code	B2
Filing date	Jun 1, 2015
Priority date	Jun 1, 2015
Publication date	Mar 14, 2017
Grant date	Mar 14, 2017

Abstract

A method for fabricating a self-aligned via structure includes forming a tri-layer mask on an ILD layer over a lower metal wiring layer, the tri-layer mask includes first and second insulating layers and a metal layer in between the insulating layers; defining a trench pattern through the first insulating layer and metal layer, the trench pattern having a first width; defining a first via pattern in a lithographic mask over the trench pattern, the first via pattern having a second width that is larger than the first width; growing a metal capping layer on an exposed sidewall of the trench pattern to decrease the first width to a third width that defines a second via pattern; transferring the trench pattern into the ILD layer to form a trench; and transferring the second via pattern through the ILD layer and into the metal wiring layer to form a via.

First claim

What is claimed is:

1. A method for fabricating a self-aligned via structure, the method comprising:
forming a tri-layer mask on an inter-level dielectric (ILD) layer, the ILD layer disposed over a lower metal wiring layer, and the tri-layer mask comprising a first insulating layer, a second insulating layer, and a metal layer disposed between the first and second insulating layers;
defining a trench pattern through the first insulating layer and the metal layer of the tri-layer mask, the trench pattern having a first width;
defining a first via pattern in a lithographic mask over the trench pattern in the tri-layer mask, the first via pattern having a second width, and the second width being larger than the first width;
growing a metal capping layer on an exposed sidewall of the trench pattern to decrease the first width of the trench pattern to a third width, the third width defining a second via pattern;
transferring the trench pattern into the ILD layer to form a trench; and
transferring the second via pattern through the ILD layer and into the metal wiring layer to form a via.

2. The method of claim 1 , wherein the metal capping layer is cobalt, cobalt tungsten phosphorus, ruthenium, titanium, titanium nitride, tantalum, tantalum nitride, tungsten, tungsten nitride, or any combination thereof.

3. The method of claim 1 , wherein the lower metal wiring layer is copper.

4. The method of claim 1 , wherein the metal capping layer is selectively formed on a portion of the metal layer within the tri-layer mask.

5. The method of claim 1 , further comprising removing the tri-layer mask and depositing a barrier metal layer into the trench and the via to form a barrier metal lining.

6. The method of claim 5 , further comprising filling the trench and the via with a metal and performing chemical mechanical planarization (CMP) to form a dual damascene structure comprising an upper wiring layer in selective contact with the lower wiring layer corresponding to locations of the vias.

7. The method of claim 6 , wherein the metal is copper.

8. The method of claim 1 , wherein the metal capping layer has a thickness in a range from about 1 nm to about 10 nanometers (nm) nm.

9. The method of claim 1 , wherein the metal layer is cobalt, cobalt tungsten phosphorus, ruthenium, titanium, titanium nitride, tantalum, tantalum nitride, tungsten, tungsten nitride, or any combination thereof.

10. The method of claim 1 , wherein the first width is in a range from about 5 nm to about 50 nm, and the second width is in a range from about 25 nm to about 70 nm.

11. The method of claim 1 , wherein the third width is in a range from about 3 nm to about 48 nm.

12. A method for fabricating a self-aligned via structure, the method comprising:
forming a tri-layer hard mask on an ILD layer, the ILD layer is disposed over a metal wiring layer, and the tri-layer hard mask comprises a first insulating layer, a second insulating layer, and a metal layer disposed between the first and second insulating layers;
forming a lithographic mask on the tri-layer hard mask;
defining a trench pattern through the first insulating layer and the metal layer of the tri-layer mask, the trench pattern having a first width;
defining a first via pattern in the lithographic mask over the trench, the first via pattern having a second width, and the second width being larger than the first width;
growing a metal capping layer selectively on a portion of the metal layer within the trench pattern to decrease the first width to a third width, the third width defining a second via pattern;
transferring the trench pattern into the ILD layer to form a trench; and
transferring the second via pattern through the ILD layer and into the metal wiring layer to form a via.

13. The method of claim 12 , wherein the via is substantially perpendicular to the trench.

14. The method of claim 12 , further comprising removing the tri-layer mask and depositing a barrier metal layer into the trench and the via to form a barrier metal lining.

15. The method of claim 14 , further comprising filling the trench and the via with copper and performing CMP to form a dual damascene structure.

Assignees

• IBM

Inventors

• Chen Hsueh-Chung H
• He Hong
• Li Juntao
• Yang Chih-Chao
• Yin Yunpeng

Classifications

• H10P50/73 Primary

  using masks for insulating materials · CPC title

• H10W20/425

  Barrier, adhesion or liner layers · CPC title

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10W20/088

  involving partial etching of via holes · CPC title

• H10W20/087

  involving multiple stacked pre-patterned masks · CPC title