Methods for forming a silicon substrate with reduced grown-in nuclei for epitaxial defects and methods for forming an epitaxial wafer

US11987900B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11987900-B2
Application numberUS-202017125590-A
CountryUS
Kind codeB2
Filing dateDec 17, 2020
Priority dateNov 11, 2020
Publication dateMay 21, 2024
Grant dateMay 21, 2024

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  1. Title

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  2. Abstract

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  4. Key dates

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  5. First independent claim

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Abstract

Official abstract text for this publication.

Methods for preparing single crystal silicon substrates for epitaxial growth are disclosed. The methods may involve control of the (i) a growth velocity, v, and/or (ii) an axial temperature gradient, G, during the growth of an ingot segment such that v/G is less than a critical v/G and/or is less than a value of v/G that depends on the boron concentration of the ingot. Methods for preparing epitaxial wafers are also disclosed.

First claim

Opening claim text (preview).

What is claimed is: 1. A method for forming a silicon substrate with reduced grown-in nuclei for epitaxial defects, the method comprising: adding an initial charge of polycrystalline silicon to a crucible disposed in an ingot puller apparatus; heating the crucible comprising the initial charge of polycrystalline silicon to cause a silicon melt to form in the crucible; adding a single dopant to the crucible, the single dopant being boron, boron being added to the crucible to prepare a doped silicon melt having a boron concentration of at least 3.8×10 18 atoms/cm 3 ; contacting a silicon seed crystal with the doped silicon melt; withdrawing the silicon seed crystal to grow a single crystal silicon ingot, the ingot having a constant diameter portion; controlling (i) a growth velocity, v, and/or (ii) an axial temperature gradient, G, during the growth of a segment of the constant diameter portion of the ingot having a boron concentration of less than 8.0×10 18 atoms/cm 3 , the ratio of v/G being controlled such that the ratio v/G is less than a critical v/G and interstitials are the dominant intrinsic point defect in the segment; pulling the segment through a hotzone of the ingot puller apparatus, the segment of the constant diameter portion of the ingot being cooled from its solidification temperature to 950° C. or less as the segment is pulled through the hotzone, wherein the dwell time the segment of the constant diameter portion of the ingot is in the temperature range from 1150° C. to 950° C. is less than 160 minutes; and slicing the substrate from the single crystal silicon ingot. 2. The method as set forth in claim 1 wherein the constant diameter portion has a length D, the length of the segment being at least 0.9*D. 3. The method as set forth in claim 1 wherein the dwell time the segment of the constant diameter portion of the ingot is in the temperature range from 1150° C. to 950° C. is less than 90 minutes. 4. The method as set forth in claim 1 wherein the concentration of boron in the segment of the constant diameter portion is from 2.8×10 18 atoms/cm 3 to 5.4×10 18 atoms/cm 3 , the (i) a growth velocity, v, and/or (ii) an axial temperature gradient, G, being controlled such that v/G is less than 0.20 mm 2 /(min*K). 5. The method as set forth in claim 1 wherein the length of the segment is the entire constant diameter portion of the ingot. 6. A method for preparing an epitaxial structure, the method comprising: forming a silicon substrate by the method of claim 1 ; and contacting a front surface of the silicon substrate with a silicon-containing gas, the silicon-containing gas decomposing to form an epitaxial silicon layer on the silicon substrate. 7. The method as set forth in claim 1 wherein the concentration of boron in the segment of the constant diameter portion is from 5.4×10 18 atoms/cm 3 to 8.0×10 18 atoms/cm 3 , the (i) a growth velocity, v, and/or (ii) an axial temperature gradient, G, being controlled such that v/G is less than 0.25 mm 2 /(min*K).

Assignees

Inventors

Classifications

  • C30B29/06Primary

    Silicon · CPC title

  • Pulling on a substrate · CPC title

  • adding doping materials, e.g. for n-p-junction · CPC title

  • Heating of the melt or the crystallised materials · CPC title

  • C30B15/203Primary

    the relationship of pull rate (v) to axial thermal gradient (G) · CPC title

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What does patent US11987900B2 cover?
Methods for preparing single crystal silicon substrates for epitaxial growth are disclosed. The methods may involve control of the (i) a growth velocity, v, and/or (ii) an axial temperature gradient, G, during the growth of an ingot segment such that v/G is less than a critical v/G and/or is less than a value of v/G that depends on the boron concentration of the ingot. Methods for preparing epi…
Who is the assignee on this patent?
Globalwafers Co Ltd
What technology area does this patent fall under?
Primary CPC classification C30B29/06. Mapped technology areas include Chemistry & Metallurgy.
When was this patent published?
Publication date Tue May 21 2024 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).