Method of embedding low-k materials in antennas

Patent metadata

Field	Value
Publication number	US-11984668-B2
Application number	US-202117360242-A
Country	US
Kind code	B2
Filing date	Jun 28, 2021
Priority date	Nov 30, 2012
Publication date	May 14, 2024
Grant date	May 14, 2024

Abstract

A device includes a patch antenna, which includes a feeding line, and a ground panel over the feeding line. The ground panel has an aperture therein. A low-k dielectric module is over and aligned to the aperture. A patch is over the low-k dielectric module.

First claim

What is claimed is:

1. A method comprising:
placing a device die and a low-k dielectric module over a first carrier;
encapsulating the device die and the low-k dielectric module in an encapsulant;
simultaneously forming a ground panel and a feeding line overlying the encapsulant, wherein the feeding line and the ground panel are in contact with the low-k dielectric module, and the feeding line and the ground panel form portions of a patch antenna; and
forming a patch of the patch antenna, wherein the patch is on a top side of the low-k dielectric module, and wherein the ground panel and the feeding line are connected to the device die on a bottom side of the low-k dielectric module.

2. The method of claim 1 , wherein the simultaneously forming the ground panel and the feeding line comprises:
depositing a metal layer; and
patterning the metal layer to form the ground panel and the feeding line.

3. The method of claim 1 , wherein the ground panel has a rectangular shaped contour, with an opening extending from a side into the rectangular shaped contour, wherein the feeding line extends into the opening.

4. The method of claim 1 further comprising, after the encapsulating, planarizing the encapsulant, until the low-k dielectric module is revealed.

5. The method of claim 4 , wherein after the low-k dielectric module is revealed, the device die is underlying and covered by a layer of the encapsulant.

6. The method of claim 5 further comprising etching the layer of the encapsulant to form a plurality of openings penetrating through the layer of the encapsulant, with conductive features of the device die revealed through the plurality of openings.

7. The method of claim 6 further comprising forming a redistribution line connecting the ground panel to the device die, wherein the redistribution line extends into one of the plurality of openings in the encapsulant.

8. The method of claim 1 , wherein a top portion of the ground panel contacts a bottom surface of the low-k dielectric module.

9. The method of claim 1 , wherein the feeding line is in physical contact with the encapsulant.

10. A method comprising:
encapsulating a device die and a low-k dielectric block in an encapsulant;
after the encapsulating, planarizing the encapsulant, until the low-k dielectric block is revealed;
forming a feeding line and a ground panel on a side of the low-k dielectric block, wherein the feeding line is connected to the device die;
forming a conductive patch, wherein the conductive patch is on an opposite side of the low-k dielectric block and an encapsulant than the feeding line and the ground panel, wherein the conductive patch contacts the low-k dielectric block, and each of the ground panel and the feeding line is in contact with the encapsulant;
embedding the conductive patch in a first dielectric layer; and

embedding the ground panel and the feeding line in a second dielectric layer, wherein the first dielectric layer and the second dielectric layer are both in contact with the encapsulant, and are on opposite sides of the encapsulant.

11. The method of claim 10 , wherein the low-k dielectric block has a dielectric constant lower than a dielectric constant of the encapsulant.

12. The method of claim 10 , wherein each of the ground panel and the feeding line is further in physical contact with the low-k dielectric block.

13. The method of claim 10 , wherein the connecting the feeding line and the forming the feeding line and the ground panel are performed in a common process.

14. The method of claim 10 , wherein the low-k dielectric block overlaps an end portion of the feeding line, and the low-k dielectric block further extends beyond the end portion of the feeding line.

15. A method comprising:
molding a dielectric block in a molding compound;
depositing a metal layer over and in physical contact with the dielectric block and the molding compound;
patterning the metal layer to form a feeding line and a ground panel, wherein each of the feeding line and the ground panel comprises a first portion over and contacting the dielectric block, and a second portion over and contacting the molding compound, wherein the feeding line is further electrically connected to a device die, wherein the ground panel has a rectangular shaped contour, with an opening extending from a side into the rectangular shaped contour, and wherein the feeding line extends into the opening; and
forming a conductive patch directly on a surface of the dielectric block, wherein the conductive patch and the feeding line are on opposite sides of the dielectric block.

16. The method of claim 15 further comprising:
molding the device die in the molding compound;
etching the molding compound to form openings in the molding compound, wherein electrical connectors of the device die are revealed through the openings; and
forming metal bumps filling the openings, wherein the feeding line is formed over and contacting one of the metal bumps.

17. The method of claim 15 , wherein the dielectric block is a low-k dielectric module.

18. The method of claim 15 , wherein edges of the conductive patch are laterally recessed from corresponding edges of the dielectric block.

19. The method of claim 15 , wherein an end of the feeding line is between a first edge and a second edge of the dielectric block.

20. The method of claim 15 further comprising:
forming the dielectric block; and
placing the dielectric block over a carrier, wherein the molding compound is molded over the carrier after the dielectric block is placed over the carrier.

Assignees

• Taiwan Semiconductor Mfg Co Ltd
• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Liu Monsen
• Chih Lai Wei
• Tsai Chung-Hao
• Hsieh Jeng-Shien
• Yeh En-Hsiang
• Wang Chuei-Tang

Classifications

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W74/019

  using temporary auxiliary substrates (H10W74/017 takes precedence) · CPC title

• H10W72/241

  Dispositions, e.g. layouts · CPC title

• H10W70/093

  Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps · CPC title

• H10W44/248

  for antennas · CPC title