Semiconductor package having a chip carrier with a pad offset feature

Patent metadata

Field	Value
Publication number	US-11984392-B2
Application number	US-202117459296-A
Country	US
Kind code	B2
Filing date	Aug 27, 2021
Priority date	Sep 28, 2020
Publication date	May 14, 2024
Grant date	May 14, 2024

Abstract

A semiconductor package includes: a carrier having an electrically insulative body and a first contact structure at a first side of the electrically insulative body; and a semiconductor die having a first pad attached to the first contact structure of the carrier, the first pad being at source or emitter potential. The first pad is spaced inward from an edge of the semiconductor die by a first distance. The semiconductor die has an edge termination region between the edge and the first pad. The first contact structure of the carrier is spaced inward from the edge of the semiconductor die by a second distance greater than the first distance such that an electric field that emanates from the edge termination region in a direction of the carrier during normal operation of the semiconductor die does not reach the first contact structure of the carrier. Methods of production are also provided.

First claim

What is claimed is:

1. A semiconductor package, comprising:
a carrier having an electrically insulative body and a first contact structure at a first side of the electrically insulative body; and
a semiconductor die having a first pad attached to the first contact structure of the carrier, the first pad being at source or emitter potential,
wherein the first pad is spaced inward from an edge of the semiconductor die by a first distance,
wherein the semiconductor die has an edge termination region between the edge and the first pad,
wherein the first contact structure of the carrier is spaced inward from the edge of the semiconductor die by a second distance greater than the first distance such that an electric field that emanates from the edge termination region in a direction of the carrier during normal operation of the semiconductor die does not reach the first contact structure of the carrier.

2. The semiconductor package of claim 1 , wherein:
the carrier has a conductive structure at a second side of the electrically insulative body opposite the first side;
the conductive structure is electrically connected to the first contact structure and covers at least part of the edge termination region of the semiconductor die; and
the carrier has a thickness between the first and second sides of the electrically insulative body that satisfies a clearance requirement between the edge termination region of the semiconductor die and the conductive structure of the carrier.

3. The semiconductor package of claim 2 , wherein the thickness of the carrier between the first and second sides of the electrically insulative body is in a range of 100 μm to 800 μm.

4. The semiconductor package of claim 1 , wherein the area of a surface of the first contact structure of the carrier that faces the first pad of the semiconductor die is smaller than the area of a surface of the first pad of the semiconductor die that faces the first contact structure of the carrier.

5. The semiconductor package of claim 1 , wherein the carrier is a direct copper bonded substrate, an active metal brazed substrate, or an insulated metal substrate having a patterned metallization at the first side of the electrically insulative body, and wherein the first patterned metallization includes the first contact structure of the carrier.

6. The semiconductor package of claim 1 , wherein:
the carrier is a pre-molded carrier having a copper block embedded in an electrically insulative material;
a first side of the copper block is uncovered by the electrically insulative material and forms the first contact structure of the carrier;
a second side of the copper block opposite the first side of the copper clock is uncovered by the electrically insulative material and forms a conductive structure at a second side of the electrically insulative body opposite the first side and that covers at least part of the edge termination region of the semiconductor die; and
the electrically insulative material has a thickness between the edge termination region of the semiconductor die and the conductive structure at the second side of the electrically insulative body that satisfies a clearance requirement between the edge termination region and the conductive structure.

7. The semiconductor package of claim 1 , wherein:
the carrier is a printed circuit board (PCB) having a first patterned metallization at the first side of the electrically insulative body and a second patterned metallization at a second side of the electrically insulative body opposite the first side;
the first patterned metallization includes the first contact structure of the carrier;
the second patterned metallization includes a conductive structure that covers at least part of the edge termination region of the semiconductor die;
the conductive structure is electrically connected to the first contact structure by a plurality of electrically conductive vias that extend through the electrically insulative body; and
the PCB has a thickness between the first and second sides of the electrically insulative body that satisfies a clearance requirement between the edge termination region of the semiconductor die and the conductive structure formed in the second patterned metallization.

8. The semiconductor package of claim 1 , wherein:
the first contact structure of the carrier comprises a plurality of electrically conductive vias attached to the first pad of the semiconductor die and that extend through the electrically insulative body to a second side of the electrically insulative body;
the plurality of electrically conductive vias are connected to a patterned metallization at the second side of the electrically insulative body;
the patterned metallization includes a conductive structure that covers at least part of the edge termination region of the semiconductor die; and
the carrier has a thickness between the first and second sides of the electrically insulative body that satisfies a clearance requirement between the edge termination region of the semiconductor die and the conductive structure formed in the patterned metallization at the second side of the electrically insulative body of the carrier.

9. The semiconductor package of claim 1 , wherein the carrier has a second contact structure at the first side of the electrically insulative body, wherein the second contact structure is electrically insulated from the first contact structure, wherein the semiconductor die has a second pad attached to the second contact structure of the carrier, and wherein the second pad is a control terminal pad.

10. The semiconductor package of claim 1 , further comprising:
a metal plate attached to a pad at a side of the semiconductor die that faces away from the carrier.

11. The semiconductor package of claim 10 , wherein outside a periphery of both the semiconductor die and the carrier, the metal plate is bent at only one end in a direction toward the carrier to provide a terminal for the pad at the side of the semiconductor die that faces away from the carrier.

12. The semiconductor package of claim 10 , wherein the metal plate has a size that is independent of a size of the carrier and based on an expected thermal load to be presented by the semiconductor die.

13. The semiconductor package of claim 10 , further comprising:
an encapsulant laterally surrounding the edge of the semiconductor die.

14. The semiconductor package of claim 13 , wherein the encapsulant fills a gap between the edge termination region of the semiconductor die and the electrically insulative body of the carrier.

15. A method of producing a semiconductor package, the method comprising:
providing a carrier having an electrically insulative body and a first contact structure at a first side of the electrically insulative body; and
attaching a first pad of a semiconductor die to the first contact structure of the carrier, the first pad being at source or emitter potential,
wherein the first pad is spaced inward from an edge of the semiconductor die by a first distance,
wherein the semiconductor die has an edge termination region between the edge and the first pad,
wherein the first contact structure of the carrier is spaced inward from the edge of the semiconductor die by a second distance greater than the first distance such that an electric field that emanates from the edge termination region in a direction of the carrier during normal operation of the semiconductor die does not reach the first contact structure of the carrier.

16. The method of claim 15 , wherein:
the carrier has a conductive structur

Assignees

• Infineon Technologies Ag

Inventors

• Ng Chee Yang
• Woetzel Stefan
• Fuergut Edward
• Gan Thai Kee
• Lee Chee Hong
• Narayanasamy Jayaganasan
• Otremba Ralf

Classifications

• H10W72/877

  Bump connectors and die-attach connectors · CPC title

• H10W72/944

  Dispositions of multiple bond pads · CPC title

• H10W72/9413

  on encapsulations · CPC title

• H10W72/20

  Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title