Asynchronous consensus circuit with stacked linear or paraelectric planar capacitors

Patent metadata

Field	Value
Publication number	US-11979148-B2
Application number	US-202217648115-A
Country	US
Kind code	B2
Filing date	Jan 14, 2022
Priority date	Jan 13, 2022
Publication date	May 7, 2024
Grant date	May 7, 2024

Abstract

Asynchronous circuit elements are described. Asynchronous circuit elements include a consensus element (c-element), completion tree, and validity tree. The c-element is implemented using adjustable threshold based multi-input capacitive circuitries. The completion tree comprises a plurality of c-elements organized in a tree formation. The validity tree comprises OR gates followed by c-elements. The multi-input capacitive circuitries include capacitive structures that may comprise linear dielectric, paraelectric dielectric, or ferroelectric dielectric. The capacitors can be planar or non-planar. The capacitors may be stacked vertically to reduce footprint of the various asynchronous circuitries.

First claim

We claim:

1. An apparatus comprising:
a first input;
a second input; and
a consensus circuitry coupled to the first input and the second input, wherein the consensus circuitry is to generate a consensus output which is indicative of a consensus of the first input and the second input, wherein the consensus circuitry comprises a gate to receive the first input, the second input, and a third input, wherein and the third input is coupled to an output of the gate which is the consensus output, and wherein the gate comprises:
a first capacitor having a first terminal coupled to the first input, and a second terminal coupled to a summing node;
a second capacitor having a third terminal coupled to the second input, and a fourth terminal coupled to the summing node; and
a third capacitor having a fifth terminal coupled to the third input, and a sixth terminal coupled to the summing node, wherein the first capacitor, the second capacitor, and the third capacitor are planar stacked capacitors.

2. The apparatus of claim 1 comprising a circuitry to adjust logic levels of the first input, the second input, and a control in a first operation mode.

3. The apparatus of claim 2 , wherein the gate comprises a device coupled to the summing node and a supply rail, wherein the device is controllable by the control, wherein the circuitry is to adjust a function of the gate in the first operation mode, and wherein the circuitry is to allow the gate to operate in accordance with the function in a second operation mode.

4. The apparatus of claim 3 , wherein the function is a majority function.

5. The apparatus of claim 3 , wherein the device is a pull-up device coupled to the summing node and a power supply rail.

6. The apparatus of claim 5 , wherein the circuitry is to set logic levels of the first input, the second input, and the third input to logic high, and the control to enable or turn on the pull-up device in the first operation mode to adjust a threshold of the gate to 2.

7. The apparatus of claim 5 , wherein the pull-up device is controlled by the control, wherein voltages on the first input, the second input, and the control are set in the first operation mode to adjust a threshold of the apparatus, wherein the control is to cause the pull-up device to be off in the second operation mode, and wherein the second operation mode occurs after the first operation mode.

8. The apparatus of claim 1 , wherein the first capacitor, the second capacitor, and the third capacitor comprise linear dielectric material or paraelectric material.

9. The apparatus of claim 1 , wherein the gate comprises:
a first metal layer that extends along an x-plane;
a second metal layer that extends along the x-plane, wherein the second metal layer is above the first metal layer;
a first via that extends along a y-plane, wherein the y-plane is orthogonal to the x-plane, and wherein the first via couples the first metal layer with the second metal layer;
a second via that extends along the y-plane, wherein the second via couples the second metal layer, and wherein the second via is above the first via;
a first pedestal on the first metal layer, wherein the first pedestal is laterally offset from the first via;
a second pedestal on the second metal layer, wherein the second pedestal is laterally offset from the second via, and wherein the summing node is coupled to the first via;
a first input line that extends along a z-plane, wherein the z-plane is orthogonal to the x-plane and the y-plane, and wherein the first input is coupled to the first input line; and
a second input line that extends along the z-plane, wherein the second input is coupled to the second input line.

10. The apparatus of claim 9 , wherein the first capacitor comprises a first planar stack of materials including a first linear dielectric material or a first paraelectric material, wherein the first planar stack of materials has a first top electrode and a first bottom electrode, wherein the first linear dielectric material or the first paraelectric material is between the first top electrode and the first bottom electrode, wherein the first bottom electrode is on the first pedestal, and wherein the first input line is on the first top electrode.

11. The apparatus of claim 10 , wherein the second capacitor comprises a second planar stack of materials including a second linear dielectric material or a second paraelectric material, wherein the second planar stack of materials has a second top electrode and a second bottom electrode, wherein the second linear dielectric material or the second paraelectric material is between the second top electrode of the second planar stack of materials and the second bottom electrode and the second planar stack of materials, wherein the second bottom electrode is on the second pedestal, and wherein the second input line is on the second top electrode of the second planar stack of materials.

12. The apparatus of claim 10 , wherein the first linear dielectric material includes one of: SiO 2 Al 2 O 3 , Li 2 O, HfSiO 4 , Sc 2 O 3 , SrO, HfO 2 , ZrO 2 , Y 2 O 3 , Ta 2 O 5 , BaO, WO 3 , MoO 3 , or TiO 2 .

13. The apparatus of claim 1 , wherein the first capacitor, the second capacitor, or the third capacitor include:
a linear dielectric material includes one or more of: Si, Al, Li, Hf, Sc, Sr, Zr, Y, Ta, Ba, W, Mo, or Ti; and
a top electrode and a bottom electrode, wherein the linear dielectric material is between the top electrode and the bottom electrode, and wherein the top electrode or the bottom electrode include one or more of: Cu, Al, Ag, Au, W, or Co.

14. The apparatus of claim 1 , wherein the first capacitor, the second capacitor, or the third capacitor include paraelectric material which includes one of: SrTiO 3 , TiO 3 with Ba and Sr, HfZrO 2 , Hf-Si-O, BaTiO 3 , La-substituted PbTiO 3 , lead zirconate titanate, or PMN-PT (lead magnesium niobate-lead titanate) based relaxor ferroelectrics.

15. An apparatus comprising:
a first input;
a second input;
a third input;
a fourth input;
a fifth input; and
a gate to provide an output which is a consensus of the first input, the second input, and the third input,
wherein:
the output is coupled to the fourth input and the fifth input,

the gate has a plurality of capacitors that are planar capacitors, and
the planar capacitors are vertically stacked.

16. The apparatus of claim 15 , wherein the output is a logic high when the first input, the second input, and the third input are logic high, wherein the output is a logic low when the first input, the second input, and the third input are logic low, wherein the output retains its logic state when at least one of the first input, the second input, or the third input is a logic 1 and when at least one of the first input, the second input, or the third input is a logic 0.

17. The apparatus of claim 15 , wherein the gate comprises:
a first capacitor having a first terminal coupled to the first input, and a second terminal coupled to a summing node;
a second capacitor having a third terminal coupled to the second input, and a fourth terminal coupled to the summing node;
a third capacitor having a fifth terminal coupled to the third input, and a sixth terminal coupled to the summing node;
a fourth capacitor having a seventh terminal coupled to the fourth input and the fifth input, and an eighth terminal coupled to the summing node;
a fifth capacitor having a ninth terminal coupled to the fourth input and the fifth input, and a tenth terminal coupled to the summing node, wherein the first capacitor,

Assignees

• Kepler Computing Inc

Inventors

• Mathuriya Amrita
• Imam Nabil
• Odinaka Ikenna
• Rios Rafael
• Dokania Rajeev Kumar
• Manipatruni Sasikanth

Classifications

• H10P14/69398

  the material having a perovskite structure, e.g. BaTiO3 · CPC title

• H10D1/684

  the dielectrics comprising multiple layers, e.g. comprising buffer layers, seed layers or gradient layers · CPC title

• G11C11/221

  using ferroelectric capacitors · CPC title

• H10B53/30

  characterised by the memory core region · CPC title

• H03K19/0021 Primary

  Modifications of threshold (for electronic switching or gating H03K17/30) · CPC title