Diffused bitline replacement in memory

Patent metadata

Field	Value
Publication number	US-11978724-B2
Application number	US-202218145375-A
Country	US
Kind code	B2
Filing date	Dec 22, 2022
Priority date	Mar 29, 2019
Publication date	May 7, 2024
Grant date	May 7, 2024

Abstract

Techniques are disclosed herein for creating metal bitlines (BLs) in stacked wafer memory. Using techniques described herein, metal BLs are created on a bottom surface of a wafer. The metal BLs can be created using different processes. In some configurations, a salicide process is utilized. In other configurations, a damascene process is utilized. Using metal reduces the resistance of the BLs as compared to using non-metal diffused BLs. In some configurations, wafers are stacked and bonded together to form three-dimensional memory structures.

First claim

What is claimed is:

1. A memory device comprising:
a first vertical transistor array that includes a first transistor surface and a second transistor surface;
metal bitlines (BLs) coupled to the second transistor surface, wherein vertical transistors of the first vertical transistor array are electrically coupled to the metal BLs via the second transistor surface;
memory storage devices coupled to the first transistor surface;
a second vertical transistor array that includes a first transistor surface and a second transistor surface;
second metal BLs coupled to the second transistor surface; and
second memory storage devices electrically coupled to the first surface of the second vertical transistor array, wherein the second vertical transistor array is stacked and electrically coupled to the first vertical transistor array.

2. The memory device of claim 1 , further comprising diffused semiconductor bitlines between the metal BLs and the second transistor surface.

3. The memory device of claim 1 , wherein the metal BLs are vertically aligned with corresponding vertical transistors of the first vertical transistor array.

4. A memory array comprising:
a substrate;
a vertical transistor array disposed on and in the substrate, the vertical transistor array including first source/drain regions on a first side of the vertical transistor array and second source/drain regions on a second side of the vertical transistor array opposite the first side;
bitlines at least partially within the substrate on the first side of the vertical transistor array, the bitlines electrically connected to the first source/drain regions of corresponding vertical transistors of the vertical transistor array, each of the bitlines comprising at least a metal bitline portion on an opposite side of the bitline from the corresponding vertical transistor; and
memory storage devices on the second side of the vertical transistor array, the memory storage devices electrically connected to the second source/drain regions.

5. The memory array of claim 4 , wherein each of the bitlines is vertically in line with the corresponding first source/drain region.

6. The memory array of claim 5 , wherein each of the bitlines comprises a semiconductor portion adjacent a corresponding first source/drain region, and each of the metal bitline portions comprises a metal portion and a metal silicide portion between the semiconductor portion and the metal portion.

7. The memory array of claim 5 , wherein each of the bitlines is disposed in a trench.

8. The memory array of claim 5 , wherein each of the metal bitline portions comprises copper.

9. The memory array of claim 5 , wherein each of the metal bitline portions comprises cobalt.

10. The memory array of claim 5 , wherein each of the metal bitline portions comprises tungsten.

11. The memory array of claim 5 , wherein each of the metal bitline portions comprises aluminum.

12. The memory array of claim 5 , wherein each of the bitlines comprises a doped semiconductor portion between the corresponding metal bitline portion and the corresponding first source/drain region.

13. The memory array of claim 12 , wherein each of the metal bitline portions comprises a metal portion and a silicide portion between the corresponding metal portion and the corresponding doped semiconductor portion.

14. The memory array of claim 12 , wherein each of the bitlines further comprises a barrier layer disposed between the doped semiconductor portion and the corresponding metal bitline portion.

15. The memory array of claim 4 , wherein each of the bitlines is vertically in line with the corresponding second source/drain region.

16. The memory array of claim 15 , wherein each of the bitlines comprises a semiconductor portion adjacent a corresponding first source/drain region, and each of the metal bitline portions comprises a metal portion, and a metal silicide portion between the semiconductor portion and the metal portion.

17. The memory array of claim 15 , wherein each of the bitlines is disposed in a trench.

18. The memory array of claim 15 , wherein each of the metal bitline portions comprises copper.

19. The memory array of claim 15 , wherein each of the metal bitline portions comprises cobalt.

20. The memory array of claim 15 , wherein each of the metal bitline portions comprises tungsten.

21. The memory array of claim 15 , wherein each of the metal bitline portions comprises aluminum.

22. The memory array of claim 15 , wherein each of the bitlines comprises a doped semiconductor portion between the corresponding metal bitline portion and the corresponding first source/drain region.

23. The memory array of claim 22 , wherein each of the metal bitline portions comprises a metal portion and a silicide portion between the corresponding metal portion and the corresponding doped semiconductor portion.

24. The memory array of claim 22 , wherein each of the bitlines further comprises a barrier layer disposed between the doped semiconductor portion and the corresponding metal bitline portion.

25. The memory array of claim 4 , further comprising low-k dielectric regions separating at least portions of the bitlines.

26. The memory array of claim 4 , wherein each of the vertical transistors of the vertical transistor array comprises a vertical pillar transistor in line with a corresponding one of the bitlines.

27. A semiconductor device, comprising:
a first substrate;
a vertical transistor array disposed in and on the first substrate, the vertical transistor array having a first side and a second side opposite the first side;
bitlines at least partially disposed in the first substrate on a first side of the vertical transistor array, the bitlines being electrically connected to first source/drain regions of the vertical transistor array on the first side of the vertical transistor array, the bitlines comprising at least metal bitline portions on an opposite side of the bitlines from the vertical transistor array;
memory storage devices disposed on the second side of the vertical transistor array, wherein the memory storage devices are electrically connected to second source/drain regions of the vertical transistor array on the second side of the vertical transistor array; and
a second substrate, wherein the vertical transistor array is electrically coupled to second transistors of the second substrate.

28. The semiconductor device of claim 27 , wherein the second substrate comprises a second vertical transistor array.

Assignees

• Adeia Semiconductor Tech Llc

Inventors

• Morein Stephen

Classifications

• H10P52/403

  of conductive or resistive materials · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/26

  the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape · CPC title

• H10W20/081

  by forming openings in the dielectric parts · CPC title