Forming contact holes with controlled local critical dimension uniformity

Patent metadata

Field	Value
Publication number	US-11978631-B2
Application number	US-202017116911-A
Country	US
Kind code	B2
Filing date	Dec 9, 2020
Priority date	Dec 9, 2020
Publication date	May 7, 2024
Grant date	May 7, 2024

Abstract

A method for forming a device includes forming a hole pattern in a resist layer disposed over a substrate. The substrate includes contact regions disposed over a major surface of the substrate and a dielectric layer disposed over the contact regions. The resist layer is disposed over the dielectric layer and the hole pattern includes through openings in the resist layer that are aligned with the contact regions. The through openings include a first through opening having a first critical dimension and a second through opening having a second critical dimension greater than the first critical dimension. The method includes modifying the hole pattern by depositing a material including silicon within the through openings by exposing the hole pattern to a first plasma generated from a gas mixture including SiCl 4 and hydrogen, and then etching holes in the dielectric layer through the modified hole pattern, exposing the contact regions.

First claim

What is claimed is:

1. A method of forming a semiconductor device, the method comprising:
forming a hole pattern in a resist layer disposed over a substrate, the substrate comprising contact regions disposed over a major surface of the substrate and a dielectric layer disposed over the contact regions, the resist layer being disposed over the dielectric layer, the hole pattern comprising through openings in the resist layer that are aligned with the contact regions;
modifying the hole pattern by depositing a material comprising silicon within the through openings by exposing the hole pattern to a first plasma generated from a gas mixture comprising SiCl 4 and hydrogen, wherein the through openings comprise a first through opening having a first critical dimension and a second through opening having a second critical dimension greater than the first critical dimension, and wherein a first thickness of the material deposited on sidewalls of the first through opening is greater than a second thickness of the material deposited on sidewalls of the second through opening; and
etching holes in the dielectric layer by exposing the dielectric layer to a second plasma through the modified hole pattern, the holes exposing the contact regions.

2. The method of claim 1 , wherein a thickness of the material comprising silicon deposited on sidewalls of the through openings is greater than a thickness of the material deposited on bottom surfaces of the through openings.

3. The method of claim 1 , wherein the hole pattern has a first local critical dimension uniformity value based on critical dimensions of the through openings, wherein the modified hole pattern has a second local critical dimension uniformity value based on critical dimensions of the through openings with the material comprising silicon, wherein the first local critical dimension uniformity value is greater than the second local critical dimension uniformity value.

4. The method of claim 1 , wherein the resist layer is an extreme ultraviolet (EUV) photoresist layer or an e-beam photoresist layer and wherein forming the hole pattern comprises:
exposing the resist layer to EUV light or an e-beam; and
developing the resist layer after the exposing to form the hole pattern.

5. The method of claim 1 , further comprising filling the holes with a conductive material to form a contact plug or via.

6. The method of claim 1 , further comprising performing a descum process by exposing the hole pattern to a third plasma prior to exposing the hole pattern to the first plasma.

7. The method of claim 1 , further comprising exposing the modified hole pattern to a plasma trim process and removing the material comprising silicon from bottom surfaces of the through openings to expose the bottom surfaces of the through openings.

8. The method of claim 1 , further comprising:
forming a hard mask layer between the resist layer and the dielectric layer;
forming a bottom antireflective coating (BARC) layer between the resist layer and the hard mask layer; and
prior to forming holes in the dielectric layer, forming a etch mask by transferring the hole pattern to the hard mask layer through the BARC layer, wherein forming holes in the dielectric layer comprises using the etch mask to form the holes.

9. The method of claim 8 , wherein the BARC layer comprises a silicon antireflective coating (ARC) layer, an organic ARC layer, a metal ARC layer, a metal oxide ARC layer, or a titanium nitride ARC layer, and wherein the hard mask layer comprises a silicon antireflective coating layer, a metal layer, a metal oxide layer, titanium nitride, or tantalum nitride.

10. The method of claim 1 , further comprising:
measuring the critical dimensions of the through openings;
determining a first local critical dimension uniformity value based on the critical dimensions of the through openings;
measuring the critical dimensions of the through openings with the material comprising silicon;
determining a second local critical dimension uniformity value based on the critical dimensions of the through openings with the material comprising silicon;
generating a set of process parameters by adjusting process parameters of the first plasma based on a difference between the second local critical dimension uniformity value and a target local critical dimension uniformity value; and
performing the steps of forming the hole pattern, modifying the hole pattern, and etching the holes in another substrate with the first plasma modified with the set of process parameters.

11. A method of forming a semiconductor device, the method comprising:
forming a hole pattern in a resist layer disposed over a substrate, the substrate comprising contact regions disposed over a major surface of the substrate and a dielectric layer disposed over the contact regions, the resist layer being disposed over the dielectric layer, the hole pattern comprising through openings in the resist layer that are aligned with the contact regions;
modifying the hole pattern by depositing a material comprising silicon within the through openings by exposing the hole pattern to a first plasma generated from a gas mixture comprising SiCl 4 and hydrogen; and
measuring critical dimensions of the through openings with the material comprising silicon;
determining a local critical dimension uniformity value based on the critical dimensions of the through openings with the material comprising silicon;
generating a set of process parameters by adjusting process parameters of the first plasma based on a difference between the local critical dimension uniformity value and a target local critical dimension uniformity value;
on further substrates, repeating the steps of forming the hole pattern, modifying the hole pattern with the first plasma using the generated set of process parameters, measuring the critical dimensions of the through openings with the material comprising silicon, determining the local critical dimension uniformity value, generating the set of process parameters until the local critical dimension uniformity value reaches a target local critical dimension uniformity value;
performing the steps of forming the hole pattern in another substrate and modifying the hole pattern with the first plasma using the generated set of process parameters; and
etching holes in the dielectric layer by exposing the dielectric layer to a second plasma through the modified hole pattern, the holes exposing the contact regions.

12. The method of claim 11 , wherein a thickness of the material comprising silicon deposited on sidewalls of the through openings is greater than a thickness of the material deposited on bottom surfaces of the through openings.

13. The method of claim 11 , wherein the through openings comprise a first through opening having a first critical dimension and a second through opening having a second critical dimension greater than the first critical dimension, and wherein a first thickness of the material deposited on sidewalls of the first through opening is greater than a second thickness of the material deposited on sidewalls of the second through opening.

14. The method of claim 11 , further comprising performing a descum process by exposing the hole pattern to a third plasma prior to exposing the hole pattern to the first plasma.

15. The method of claim 11 , further comprising exposing the modified hole pattern to a plasma trim process and removing the material comprising silicon from bottom surfaces of the through openings to expose the bottom surfaces of the through openings.

16. The method of claim 11 , fu

Assignees

• Tokyo Electron Ltd

Inventors

• Sun Junling
• Lutker-Lee Katie
• Raley Angelique
• Metz Andrew

Classifications

• H10P76/2049

  Ion beam lithography processes · CPC title

• H10P76/2043

  using an anti-reflective coating · CPC title

• H10P70/234

  the processing being the formation of vias or contact holes · CPC title

• H10P76/4088

  Processes for improving the resolution of the masks · CPC title

• H10P74/203

  Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects · CPC title