Latch circuit and equalizer including the same

Patent metadata

Field	Value
Publication number	US-11973623-B2
Application number	US-202217834563-A
Country	US
Kind code	B2
Filing date	Jun 7, 2022
Priority date	Jun 11, 2021
Publication date	Apr 30, 2024
Grant date	Apr 30, 2024

Abstract

A latch circuit and an equalizer including the same are provided. The equalizer includes: an even data path configured to receive a reception data signal and including a first summing circuit and a first latch circuit; and an odd data path configured to receive the reception data signal and including a second summing circuit and a second latch circuit. An even data signal output from the first latch circuit is configured to be input to the second summing circuit, and an odd data signal output from the second latch circuit is configured to be input to the first summing circuit. Each of the first latch circuit and the second latch circuit includes a latch and a multiplexer.

First claim

What is claimed is:

1. An equalizer comprising:
an even data path configured to receive a reception data signal, and comprising a first summing circuit and a first latch circuit; and
an odd data path configured to receive the reception data signal, and comprising a second summing circuit and a second latch circuit,
wherein an even data signal output from the first latch circuit is configured to be input to the second summing circuit, and an odd data signal output from the second latch circuit is configured to be input to the first summing circuit,
each of the first latch circuit and the second latch circuit comprises a latch and a multiplexer, and
the multiplexer of the first latch circuit is configured to receive a signal that is input to the latch of the first latch circuit as a first input, receive a signal that is output from the latch as a second input, output the signal received as the first input based on data being applied to the latch, and output the signal received as the second input based on the data being maintained in the latch.

2. The equalizer of claim 1 , wherein the latch and the multiplexer of the first latch circuit are configured to operate based on an even clock signal,
the latch and the multiplexer of the second latch circuit are configured to operate based on an odd clock signal, and
the even clock signal and the odd clock signal have a same cycle and a phase difference of about 90°.

3. The equalizer of claim 2 , wherein the even clock signal comprises a first even clock signal and a second even clock signal having a same cycle and a phase difference of about 180°, and
the odd clock signal comprises a first odd clock signal and a second odd clock signal having a same cycle and a phase difference of about 180°.

4. The equalizer of claim 2 , wherein the odd data path is further configured to provide a signal from an output node of the first summing circuit to an output node of the second summing circuit in less than or equal to a half of the cycle of the even clock signal.

5. The equalizer of claim 1 , wherein the even data signal and the odd data signal are non-return to zero (NRZ) signals.

6. An equalizer comprising:
an even data path configured to receive a reception data signal, and comprising a first summing circuit and a first latch circuit; and
an odd data path configured to receive the reception data signal, and comprising a second summing circuit and a second latch circuit,
wherein an even data signal output from the first latch circuit is configured to be input to the second summing circuit, and an odd data signal output from the second latch circuit is configured to be input to the first summing circuit,
each of the first latch circuit and the second latch circuit comprises a latch and a multiplexer, and
the even data path further comprises:
a first sense amplifier configured to receive a first source amplifier input signal that is output from the first summing circuit and generate a first source amplifier output signal; and
a first buffer configured to generate a first buffer output signal based on the first source amplifier output signal and provide the first buffer output signal to the first latch circuit.

7. The equalizer of claim 6 , wherein the odd data path further comprises:
a second sense amplifier configured to receive a second source amplifier input signal that is output from the second summing circuit and generate a second source amplifier output signal; and
a second buffer configured to generate a second buffer output signal based on the second source amplifier output signal and provide the second buffer output signal to the second latch circuit.

8. An equalizer comprising an even data path configured to receive a reception data signal and generate an even data signal based on an even clock signal, wherein the even data path comprises:
a first amplifier configured to amplify the reception data signal and output a first amplification signal;
a first summing circuit configured to sum the first amplification signal and an odd data signal, and generate a first source amplifier input signal;
a first sense amplifier configured to generate a first source amplifier output signal based on the first source amplifier input signal;
a first buffer configured to generate a first buffer output signal based on the first source amplifier output signal; and
a first latch circuit including a latch and a multiplexer, and configured to generate the even data signal based on the first buffer output signal,
wherein the multiplexer of the first latch circuit is configured to receive the first buffer output signal and a latch signal, and output one of the first buffer output signal and the latch signal as the even data signal according to the even clock signal.

9. The equalizer of claim 8 , wherein the equalizer is a decision feedback equalizer (DFE).

10. The equalizer of claim 8 , wherein the latch of the first latch circuit is configured to latch the first source amplifier input signal based on the even clock signal and generate the latch signal.

11. The equalizer of claim 10 , wherein the multiplexer of the first latch circuit is further configured to output the first buffer output signal as the even data signal based on data being applied to the latch of the first latch circuit, and output the latch signal as the even data signal based on the data being maintained in the latch.

12. The equalizer of claim 8 , wherein the first summing circuit is further configured to perform weighted summation of the first amplification signal and the odd data signal.

13. The equalizer of claim 8 , further comprising an odd data path configured to receive the reception data signal and generate the odd data signal based on an odd clock signal,
wherein the odd data path further comprises:
a second amplifier configured to amplify the reception data signal and output a second amplification signal;
a second summing circuit configured to sum the second amplification signal and the even data signal, and generate a second source amplifier input signal;
a second sense amplifier configured to generate a second source amplifier output signal based on the second source amplifier input signal;
a second buffer configured to generate a second buffer output signal based on the second source amplifier output signal; and
a second latch circuit including a latch and a multiplexer, and configured to generate the odd data signal based on the second buffer output signal.

14. The equalizer of claim 13 , wherein the even clock signal and the odd clock signal have a same cycle and a phase difference of about 90°.

15. The equalizer of claim 8 , wherein the multiplexer of the first latch circuit is a transmission gate.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Ko Kyeongjoon
• Kim Hanseok
• Park Jaehyun
• Bae Junhan
• Song Gyeongseok
• Ryu Jongjae

Classifications

• H04L25/03057 Primary

  with a recursive structure (H04L25/03031 takes precedence) · CPC title

• H04B1/16 Primary

  Circuits · CPC title

• H04L25/03878

  Line equalisers; line build-out devices · CPC title

• H04L2025/03445

  Time domain · CPC title

• H04L25/03146

  with a recursive structure (H04L25/03127 takes precedence) · CPC title