Influence clock data recovery settling point by applying decision feedback equalization to a crossing sample

Patent metadata

Field	Value
Publication number	US-2016226684-A1
Application number	US-201614988675-A
Country	US
Kind code	A1
Filing date	Jan 5, 2016
Priority date	Dec 26, 2012
Publication date	Aug 4, 2016
Grant date	—

Abstract

An apparatus including a receiver coupled to receive an input signal from a communication link and operable to employ decision feedback equalization to the input signal of the communication link and generate an edge sample signal. The apparatus also includes a timing recovery module coupled to the receiver and operable to receive the edge sample signal and use the edge sample signal to generate a data sampling phase signal, wherein the edge sample signal influences a settling point of the data sampling phase signal.

First claim

1 - 20 . (canceled)

21 . An apparatus, comprising:
a first module coupled to an input signal and operable to generate an edge signal using a first clock signal; and a second module operable to receive said edge signal and further operable to generate a data sampling phase signal, wherein said edge signal influences a settling point of said data sampling phase signal.

22 . The apparatus of claim 21 , further comprising:
a third module operable to generate a data sample signal using a second clock signal; and a fourth module operable to generate an error sample signal using a third clock signal and wherein said first module is a decision feedback equalizer.

23 . The apparatus of claim 21 , wherein said first module further comprises:
a first path coupled to said input signal, said first path comprising:
a first preamplifier;
a first summing node coupled to said first preamplifier; and
a first latch coupled to said first summing node and said first clock signal;
a second path coupled to said input signal, said second path comprises:
a second preamplifier;
a summing node coupled to said second preamplifier and operable to apply feedback to its input signal based on a previously generated data sample; and
a second latch coupled to said second summing node; and
a multiplexer coupled to said first latch and said second latch, said multiplexer operable to select an output between said first latch and said second latch based on an exclusive OR of a first and a second previously generated data samples.

24 . The apparatus of claim 21 , wherein said first module further comprises:
a first path coupled to said input signal, said first path comprising:
a first preamplifier;
a first summing node coupled to said first preamplifier and operable to apply a first feedback to its input signal based on a previously generated data sample; and
a first latch coupled to said first summing node;
a second path coupled to said input signal, said second path comprising:
a second preamplifier;
a second summing node coupled to said second preamplifier and operable to apply a second feedback to its input signal based on a previously generated data sample; and
a second latch coupled to said second summing node; and
a multiplexer coupled to said first latch and said second latch, said multiplexer operable to select an output between said first latch and said second latch based on an exclusive OR of a first and a second previously generated data samples.

25 . The apparatus of claim 21 , wherein said first module further comprises:
a first path coupled to said input signal, said first path comprising:
a first preamplifier operable to offset said input signal by a first predefined constant value;
a first summing node coupled to said first preamplifier; and
a first latch coupled to said summing node;
a second path coupled to said input signal, said second path comprising:
a second preamplifier operable to offset said input signal by a second predefined constant value;
a second summing node coupled to said second preamplifier;
a second latch coupled to said second summing node; and
a multiplexer coupled to said first latch and said second latch, said multiplexer operable to select between an output of said first latch and said second latch based on a previously generated data sample.

26 . The apparatus of claim 21 , wherein said second module comprises:
a phase detector operable to receive said edge sample signal and generate a plurality of delta phases therefrom; a loop filter coupled to said phase detector operable to average said plurality of delta phases and generate a phase code; and a phase interpolator coupled to said loop filter operable to generate said data sampling phase based upon said phase code.

27 . The apparatus of claim 26 , wherein said plurality of delta phases are generated as a function of said edge sample signal, a current data sample, and a prior data sample.

28 . The apparatus of claim 21 , further comprising a plurality of said first modules, wherein each of said plurality of first modules operates on its own set of clocks.

29 . The apparatus of claim 21 , further comprising a linear equalizer configured to shape an input pulse response.

30 . An apparatus for arriving at a clock and data recovery settling point of a data sampling point signal, said apparatus comprising:
a receiver coupled to receive an input signal and operable to employ decision feedback equalization (DFE) on the input signal and operable to generate an edge sample signal therefrom using a first clock signal; and a timing recovery module coupled to said receiver and operable to receive said edge sample signal and generate a data sampling phase signal based on said edge sample signal.

31 . The receiver of claim 30 , wherein said first module comprises:
a first branch operable to apply DFE to said input signal to generate said edge sample signal using said first clock signal, wherein said edge sample signal influences a settling point of said data sampling signal; a second branch operable to generate an error sample signal using a second clock signal; and a third branch operable to generate a data sample signal using a third clock signal.

32 . The receiver of claim 30 , wherein said timing recovery module comprises:
a phase detector operable to receive said edge sample signal and generate a plurality of delta phases therefrom; a loop filter coupled to said phase detector operable to average said plurality of delta phases and generate a phase code; and a phase interpolator coupled to said loop filter operable to generate said phase code based upon values contained within a lookup table and further operable to generate said data sampling phase signal.

33 . The receiver of claim 30 , wherein said first module further comprises an odd path and an even path simultaneously processing, wherein further said odd path uses a first clock cycle and said even path uses a second clock cycle.

34 . A method comprising:
receiving an input signal at an input of a receiver; applying decision feedback equalization (DFE) to said input signal based on prior recovered data values to generate an output DFE signal; using a sample module clocked by an X clock signal, sampling said output DFE signal to generate an edge sample signal; and using said edge sample signal to influence a settling point of a data sampling signal.

35 . The method of claim 34 , wherein said using said edge sample signal further comprises:
generating a plurality of delta phases; averaging said delta phases and generating a phase code; and interpolating said phase code and generating a data sampling phase therefrom.

36 . The method of claim 34 further comprising:
offsetting said input signal by a predetermined constant.

37 . The method of claim 34 , wherein said plurality of delta phases are generated as a function of said edge sample signal, a data value, and a prior data value.

38 . The method of claim 34 , wherein said phase code is generated based upon values contained within a lookup table.

39 . The method claim 34 , further comprising:
applying decision feedback equalization (DFE) to said input signal based on prior recovered data values to generate an output DFE signal; using a sample module clocked by a data retrieval clock signal, sampling said output DFE signal to generate a data sample signal.

40 . The method of claim 34 , wherein said receiver further comprises a linea

Assignees

• Nvidia Corp

Inventors

• Zhong Lizhi
• Balan Vishnu
• Amin Arif Al
• Maheshwari Sanjeev

Classifications

• H04L7/0332

  with an integrator-detector · CPC title

• H04L27/01 Primary

  Equalisers {(baseband equalizers at the transmitter end H04L25/03343; in analogue transmission systems H04B3/04, H04B7/005)} · CPC title

• H04L25/03057 Primary

  with a recursive structure (H04L25/03031 takes precedence) · CPC title

• H04L25/03878

  Line equalisers; line build-out devices · CPC title

• H04L25/03248

  Arrangements for operating in conjunction with other apparatus · CPC title