Apparatus for processing a serial data stream

Patent metadata

Field	Value
Publication number	US-2016359645-A1
Application number	US-201514876206-A
Country	US
Kind code	A1
Filing date	Oct 6, 2015
Priority date	Jun 5, 2015
Publication date	Dec 8, 2016
Grant date	—

Abstract

A system includes a decision feedback equalizer (DFE). The DFE includes a first summing node, a first synchronization latch, a second synchronization latch, a first feedback latch, and a first feedback shift register. The first summing node is coupled to a data input of the DFE. The first synchronization latch receives data from the first summing node. The second synchronization latch and the first feedback latch receive data from the first synchronization latch. The first feedback shift register is coupled to an output of the second synchronization latch or the first feedback latch. The first feedback shift register includes sequentially coupled shift latches. A first of the shift latches data received from the second synchronization latch or the first feedback latch and provides data to the first summing node. First alternate ones of the shift latches are configured to provide feedback data to the first summing node.

First claim

What is claimed is:

1 . A decision feedback equalizer (DFE) circuit, comprising:
a first equalization path and a second equalization path, each of the first equalization path and the second equalization path comprising:
a summing node;
a first synchronization latch configured to latch data received from the summing node;
a second synchronization latch configured to latch data received from the first synchronization latch;
a feedback latch coupled to an output of the first synchronization latch and configured to latch data received from the first synchronization latch;
a feedback shift register coupled to an output of one of the second synchronization latch and the feedback latch, the feedback shift register comprising a plurality of sequentially coupled shift latches, wherein:
a first of the shift latches is configured to latch data received from one of the second synchronization latch and the feedback latch and provide data to the summing node; and
a second of the shift latches is configured to latch data received from the first of the shift latches;

wherein, in the first equalization path, the feedback latch and the second of the shift latches are configured to provide data to the summing node of the second equalization path; and, in the second equalization path, the feedback latch and the second of the shift latches are configured to provide data to the summing node of the first equalization path.

2 . The DFE circuit of claim 1 , wherein in each of the first equalization path and the second equalization path, a third of the shift latches is configured to latch data received from the second of the shift latches and provide data to the summing node of the equalization path.

3 . The DFE circuit of claim 2 , wherein in the first equalization path, a fourth of the shift latches is configured to provide data to the summing node of the second equalization path; and, in the second equalization path, a fourth of the shift latches is configured to provide data to the summing node of the first equalization path.

4 . The DFE circuit of claim 1 , wherein the feedback latch is clocked by a clock that clocks the first synchronization latch shifted by 90 degrees.

5 . The DFE circuit of claim 1 , wherein:
in the first equalization path:
the first synchronization latch is clocked by a first clock having a period that is twice the symbol interval time of the data received at the input of the DFE circuit;
the second synchronization latch is clocked by a second clock that is an inversion of the first clock; and
the first of the shift latches is clocked by a third clock that is a quadrature phase shifted version of the second clock; and
in the second equalization path:
the first synchronization latch is clocked by the second clock;
the second synchronization latch is clocked by the first clock;
the feedback shift register is clocked by a fourth clock that is an inversion of the third clock.

6 . The DFE circuit of claim 5 , further comprising a multiplexer coupled to the second synchronization latch of each equalization path, and configured to selectively route, based on the second clock, data received from the second synchronization latch of each equalization path to an output of the DFE circuit.

7 . The DFE circuit of claim 5 , further comprising a multiplexer;
wherein each of the first equalization path and the second equalization path comprises a third synchronization latch configured to latch data received from the second synchronization latch of the equalization path and to provide data to the multiplexer;
wherein the multiplexer is configured to selectively route, based on the first clock, data received from the second synchronization latch of each equalization path to an output of the DFE circuit.

8 . The DFE circuit of claim 1 wherein, in each of the first equalization path and the second equalization path, each successive one of the shift latches is clocked by a clock signal that is an inversion of a clock signal applied to an immediately preceding one of the shift latches.

9 . A system, comprising:
a decision feedback equalizer (DFE) comprising:
a first summing node coupled to a data input of the DFE;
a first synchronization latch configured to receive data from the first summing node;
a second synchronization latch configured to receive data from the first synchronization latch; and
a first feedback latch configured to receive data from the first synchronization latch;

a first feedback shift register coupled to an output of one of the second synchronization latch and the first feedback latch, the first feedback shift register comprising a plurality of sequentially coupled shift latches, wherein:
a first of the shift latches is configured to latch data received from one of the second synchronization latch and the first feedback latch and provide data to the first summing node; and
first alternate ones of the shift latches are configured to provide feedback data to the first summing node;
wherein the first summing node is configured to equalize a symbol received from the data input of the DFE by combining the data provided by first feedback latch and the first alternate ones of the shifter latches with the symbol.

10 . The system of claim 9 , wherein:
the first synchronization latch is controlled via a first clock; the second synchronization latch is controlled via a second clock that is an inverse of the first clock; the first feedback shift register is controlled via a third clock that is quadrature phase version of the second clock; the first of the shift latches is controlled via a fourth clock that is an inverse of the third clock; and each successive one of the shift latches is controlled via a clock signal that is an inverse of a clock signal applied to an immediately preceding one of the shift latches.

11 . The system of claim 10 , wherein the first clock has a period that is twice the symbol interval time of the data received at the data input of the circuit.

12 . The system of claim 9 , further comprising:
a second summing node coupled to the data input of the circuit; a third synchronization latch configured to receive data from the second summing node; a fourth synchronization latch configured to receive data from the third synchronization latch; a second feedback latch configured to receive data from the third synchronization latch; and a second feedback shift register comprising a plurality of sequentially coupled shift latches, wherein:
a first of the shift latches of the second feedback shift register is configured to latch data received from one of the fourth synchronization latch and the second feedback latch and provide data to the summing node; and
first alternate ones of the shift latches of the second feedback shift register are configured to provide feedback data to the second summing node;
wherein the second summing node is configured to equalize a symbol received from the data input of the circuit by combining the data provided by the second feedback latch, the second alternate ones of the shift latches of the first feedback shift register, and the first alternate ones of the shifter latches of the second feedback shift register with the symbol.

13 . The system of claim 12 , wherein:
the third synchronization latch is controlled via the second clock; the fourth synchronization latch is controlled via the first clock; the second feedback shift register is controlled via the fourth clock; the first of the shift latches of the second feedback shift register is controlled via an inverse of the fourth clock; and each successive one of the

Assignees

• Texas Instruments Inc

Inventors

• Mukherjee Tonmoy Shankar

Classifications

• H04L25/03057 Primary

  with a recursive structure (H04L25/03031 takes precedence) · CPC title

• H04L7/0045

  Correction by a latch cascade · CPC title

• H04L25/03878 Primary

  Line equalisers; line build-out devices · CPC title