Dynamic module and decision feedback equalizer

Patent metadata

Field	Value
Publication number	US-11044124-B1
Application number	US-202017128266-A
Country	US
Kind code	B1
Filing date	Dec 21, 2020
Priority date	Dec 21, 2020
Publication date	Jun 22, 2021
Grant date	Jun 22, 2021

Abstract

A dynamic module and a decision feedback equalizer are provided. The decision feedback equalizer includes two dynamic modules, which have symmetric circuits and connections. The dynamic module includes a first domino circuit, a second domino circuit, and a storage circuit. In response to a first previous decision bit and a second previous decision bit, a first multiplexer output and a second multiplexer output are generated. The dynamic module alternatively operates in an evaluation period and a precharge period, depending on a clock signal. In the evaluation period, the first and the second multiplexer outputs are updated by the first domino circuit and the second domino circuit. In the precharge period, the first and the second multiplexer outputs are held by the storage circuit.

First claim

What is claimed is:

1. A dynamic module, comprising:
a first domino circuit, configured for generating a first multiplexer output, comprising:
a first multiplexer, configured for receiving two of a first rail-output, a second rail-output, a third rail-output, and a fourth rail-output;
at least one first phase setting circuit, configured for receiving a first clock signal; and
a first decision selection stage, electrically connected to the first multiplexer and the at least one first phase setting circuit, configured for receiving a first previous decision bit and a second previous decision bit, wherein the first previous decision bit and the second previous decision bit are complementary; and

a second domino circuit, electrically connected to the first domino circuit, configured for generating a second multiplexer output, comprising:
a second multiplexer, configured for receiving the other two of the first rail-output, the second rail-output, the third rail-output, and the fourth rail-output;
at least one second phase setting circuit, configured for receiving a second clock signal, wherein the first clock signal and the second clock signal are complementary; and
a second decision selection stage, electrically connected to the second multiplexer and the at least one second phase setting circuit, configured for receiving the first previous decision bit and the second previous decision bit, wherein

the first and the second multiplexer outputs are selectively updated with the first rail-output, the second rail-output, the third rail-output, and the fourth rail-output in an evaluation period, and
the first multiplexer output and the second multiplexer output remain unchanged in a precharge period.

2. The dynamic module according to claim 1 , wherein
the dynamic module receives the first previous decision bit and the second previous decision bit from another dynamic module during the evaluation period, and
the dynamic module provides a third previous decision bit and a fourth previous decision bit to the another dynamic module in the precharge period, wherein
the third previous decision bit is generated based on the first multiplexer output, and
the fourth previous decision bit is generated based on the second multiplexer output.

3. The dynamic module according to claim 1 , wherein
the first rail-output and the second rail-output are provided by a first sense amplifier, and the third rail-output and the fourth rail-output are provided by a second sense amplifier, wherein
in the evaluation period, the first and second rail-outputs jointly form a first rail-to-rail output pair, and the third and fourth rail-outputs jointly form a second rail-to-rail output pair, and
in the precharge period, the first rail-output is equivalent to the second rail-output, and the third rail-output is equivalent to the fourth-rail output.

4. The dynamic module according to claim 3 , wherein
the first multiplexer receives the first rail-output from the first sense amplifier and receives the third rail-output from the second sense amplifier, and
the second multiplexer receives the second rail-output from the first sense amplifier and receives the fourth rail-output from the second sense amplifier.

5. The dynamic module according to claim 3 , wherein
the first multiplexer receives the first rail-output and the second rail-output from the first sense amplifier, and
the second multiplexer receives the third rail-output and the fourth rail-output from the second sense amplifier.

6. The dynamic module according to claim 1 , further comprising:
a storage circuit, electrically connected to the first domino circuit through a first multiplexer output terminal, and electrically connected to the second domino circuit through a second multiplexer output terminal, wherein
the first multiplexer output is generated at the first multiplexer output terminal,
the second multiplexer output is generated at the second multiplexer output terminal, and
the storage circuit holds the first multiplexer output and the second multiplexer output during the precharge period.

7. The dynamic module according to claim 6 , wherein
the at least one first phase setting circuit is electrically connected to the first multiplexer output terminal, and the at least one first phase setting circuit is controlled by the first clock signal, and
the at least one second phase setting circuit is electrically connected to the second multiplexer output terminal, and the at least one second phase setting circuit is controlled by the second clock signal.

8. The dynamic module according to claim 7 , wherein in the precharge period,
the first decision selection stage is disconnected to the first multiplexer output terminal, and
the second decision selection stage is disconnected to the second multiplexer output terminal.

9. The dynamic module according to claim 7 , wherein in the evaluation period,
the first decision selection stage is selectively electrically connected to the first multiplexer output terminal, and
the second decision selection stage is selectively electrically connected to the second multiplexer output terminal.

10. The dynamic module according to claim 1 , wherein
the first multiplexer comprises a first positive output circuit and a first negative output circuit, and
the second multiplexer comprises a second positive output circuit and a second negative output circuit, wherein in the evaluation period,
one of the first positive output circuit and the second positive output circuit generates the first multiplexer output, and
one of the first negative output circuit and the second negative output circuit generates the second multiplexer output.

11. The dynamic module according to claim 10 , wherein
when the first previous decision bit is in a first logic and the second previous decision bit is in a second logic, the first positive output circuit generates the first multiplexer output, and the first negative output circuit generates the second multiplexer output, and
when the first previous decision bit is in the second logic and the second previous decision bit is in the first logic, the second positive output circuit generates the first multiplexer output, and the second negative output circuit generates the second multiplexer output.

12. The dynamic module according to claim 10 , wherein the at least one first phase setting circuit comprises:
a first-first phase setting circuit, electrically connected to the first decision selection stage, the first positive output circuit, and the first negative output circuit, configured for receiving the first clock signal and generating a first-first selection signal; and
a second-first phase setting circuit, electrically connected to the first decision selection stage, the first positive output circuit, and the first negative output circuit, configured for receiving the second clock signal and generating a second-first selection signal.

13. The dynamic module according to claim 12 , wherein the at least one second phase setting circuit comprises:
a first-second phase setting circuit, electrically connected to the second decision selection stage, the second positive output circuit, and the second negative output circuit, configured for receiving the first clock signal and generating a first-second selection signal; and
a second-second phase setting circuit, electrically connected to the second decision selection stage, the second positive output circuit, and the second negative output circuit, configured for receiving the second clock signal and generating a second-second selection signal.

14. The dy

Assignees

• Faraday Tech Corp

Inventors

• Goyal Prateek Kumar

Classifications

• H04L25/03267 Primary

  with decision feedback equalisers · CPC title

• H04L25/03025

  using a two-tap delay line · CPC title

• H04L25/03885

  adaptive · CPC title

• H04L25/03146

  with a recursive structure (H04L25/03127 takes precedence) · CPC title

• H04L25/03057 Primary

  with a recursive structure (H04L25/03031 takes precedence) · CPC title