Source or drain structures for germanium N-channel devices

Patent metadata

Field	Value
Publication number	US-11973143-B2
Application number	US-201916368088-A
Country	US
Kind code	B2
Filing date	Mar 28, 2019
Priority date	Mar 28, 2019
Publication date	Apr 30, 2024
Grant date	Apr 30, 2024

Abstract

Integrated circuit structures having source or drain structures and germanium N-channels are described. In an example, an integrated circuit structure includes a fin having a lower fin portion and an upper fin portion, the upper fin portion including germanium. A gate stack is over the upper fin portion of the fin. A first source or drain structure includes an epitaxial structure embedded in the fin at a first side of the gate stack. A second source or drain structure includes an epitaxial structure embedded in the fin at a second side of the gate stack. Each epitaxial structure includes a first semiconductor layer in contact with the upper fin portion, and a second semiconductor layer on the first semiconductor layer. The first semiconductor layer comprises silicon, germanium and phosphorous, and the second semiconductor layer comprises silicon and phosphorous.

First claim

What is claimed is:

1. An integrated circuit structure, comprising:
a fin having a lower fin portion and an upper fin portion, the upper fin portion comprising germanium, and the upper fin portion having an uppermost surface;
a gate stack over the upper fin portion of the fin, the gate stack having a first side opposite a second side;
a first source or drain structure comprising an epitaxial structure embedded in the fin at the first side of the gate stack; and
a second source or drain structure comprising an epitaxial structure embedded in the fin at the second side of the gate stack, each epitaxial structure of the first and second source or drain structures comprising a first semiconductor layer in contact with the upper fin portion, and a second semiconductor layer on the first semiconductor layer, wherein the first semiconductor layer comprises silicon, germanium and phosphorous, and the second semiconductor layer comprises silicon and phosphorous, wherein the first semiconductor layer is at least partially along sidewalls of the second semiconductor layer, wherein the first semiconductor layer has an uppermost surface above the uppermost surface of the upper fin portion, and wherein the first semiconductor layer is graded from a higher concentration of germanium proximate the upper fin portion to a lower concentration of germanium proximate the second semiconductor layer.

2. The integrated circuit structure of claim 1 , wherein the first semiconductor layer has a thickness in the range of 5-20 nanometers.

3. The integrated circuit structure of claim 1 , wherein each epitaxial structure of the first and second source or drain structures has a phosphorous concentration in the range of 1E19 atom s/cm 3 to 5E21 atom s/cm 3.

4. The integrated circuit structure of claim 1 , wherein the first and second source or drain structures have a contact resistance of less than approximately 3E-9 Ohms/cm 2.

5. The integrated circuit structure of claim 1 , wherein the lower fin portion includes a portion of an underlying bulk single crystalline silicon substrate.

6. The integrated circuit structure of claim 1 , further comprising:
first and second dielectric gate sidewall spacers along the first and second sides of the gate stack, respectively.

7. The integrated circuit structure of claim 1 , further comprising:
a first conductive contact on the epitaxial structure of the first source or drain structure; and
a second conductive contact on the epitaxial structure of the second source or drain structure.

8. The integrated circuit structure of claim 7 , wherein the first and second conductive contacts are in a partial recess in the epitaxial structures of the first and second source or drain structures, respectively.

9. A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, comprising:
a fin having a lower fin portion and an upper fin portion, the upper fin portion comprising germanium, and the upper fin portion having an uppermost surface;
a gate stack over the upper fin portion of the fin, the gate stack having a first side opposite a second side;
a first source or drain structure comprising an epitaxial structure embedded in the fin at the first side of the gate stack; and
a second source or drain structure comprising an epitaxial structure embedded in the fin at the second side of the gate stack, each epitaxial structure of the first and second source or drain structures comprising a first semiconductor layer in contact with the upper fin portion, and a second semiconductor layer on the first semiconductor layer, wherein the first semiconductor layer comprises silicon, germanium and phosphorous, and the second semiconductor layer comprises silicon and phosphorous, wherein the first semiconductor layer is at least partially along sidewalls of the second semiconductor layer, wherein the first semiconductor layer has an uppermost surface above the uppermost surface of the upper fin portion, and wherein the first semiconductor layer is graded from a higher concentration of germanium proximate the upper fin portion to a lower concentration of germanium proximate the second semiconductor layer.

10. The computing device of claim 9 , further comprising:
a memory coupled to the board.

11. The computing device of claim 9 , further comprising:
a communication chip coupled to the board.

12. The computing device of claim 9 , further comprising:
a camera coupled to the board.

13. The computing device of claim 9 , further comprising:
a battery coupled to the board.

14. The computing device of claim 9 , wherein the component is a packaged integrated circuit die.

15. An integrated circuit structure, comprising:
a fin having a lower fin portion and an upper fin portion, the upper fin portion comprising germanium;
a gate stack over the upper fin portion of the fin, the gate stack having a first side opposite a second side;
a first source or drain structure comprising an epitaxial structure embedded in the fin at the first side of the gate stack; and
a second source or drain structure comprising an epitaxial structure embedded in the fin at the second side of the gate stack, each epitaxial structure of the first and second source or drain structures comprising a first semiconductor layer in contact with the upper fin portion, and a second semiconductor layer on the first semiconductor layer, wherein the first semiconductor layer comprises silicon, germanium and phosphorous, and the second semiconductor layer comprises silicon and phosphorous, wherein the first semiconductor layer is graded from a higher concentration of germanium proximate the upper fin portion to a lower concentration of germanium proximate the second semiconductor layer.

Assignees

• Intel Corp

Inventors

• Keech Ryan
• Chu-Kung Benjamin
• Rafique Subrina
• Merrill Devin
• Agrawal Ashish
• Kennel Harold
• Cao Yang
• Basu Dipanjan
• Torres Jessica
• Murthy Anand

Classifications

• H10P14/3444

  P-type · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10D64/62

  Electrodes ohmically coupled to a semiconductor · CPC title

• H10D64/017

  using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes · CPC title

• H10D62/834

  further characterised by the dopants · CPC title