Encoder

Patent metadata

Field	Value
Publication number	US-11962332-B2
Application number	US-202318165025-A
Country	US
Kind code	B2
Filing date	Feb 6, 2023
Priority date	Dec 10, 2019
Publication date	Apr 16, 2024
Grant date	Apr 16, 2024

Abstract

An encoding system may be provided. The encoding system may comprise a first stage and a second stage. The first stage may be configured to receive a first input, decode the first input, and produce a first output comprising the decoded first input. The second stage may be configured to receive a second input, receive the first output from the first stage, and convert the first input and the second input from a first coding system to a second coding system based on the second input and the first output. The second stage may produce a second output comprising the converted first input and the converted second input.

First claim

What is claimed is:

1. An apparatus comprising:
a first stage comprising a 7:1 decoder, wherein the 7:1 decoder decodes a first input to produce a first output; and
a second stage configured to;
receive the first output from the first stage,
receive a second input,
convert the first output and the second input from a first code to a second code based on the second input and the first output, and
a first plurality of two input port AND gates, each one of the first plurality of two input port AND gates having a first input port respectively connected to one of seven output nodes of the 7:1 decoder and a second input port connected to an inverse of an input bit.

2. The apparatus of claim 1 , wherein the first stage is configured to receive the first input.

3. The apparatus of claim 2 , wherein the first stage is configured to decode the first input.

4. The apparatus of claim 3 , wherein the first stage is configured to produce the first output comprising the decoded first input.

5. The apparatus of claim 1 , wherein the first code comprises Binary.

6. The apparatus of claim 1 , wherein the first code comprises Gray Code.

7. The apparatus of claim 1 , wherein the second code comprises Unary Code.

8. The apparatus of claim 1 , wherein the apparatus is further configured to produce a second output comprising the converted first output and the converted second input.

9. The apparatus of claim 1 , wherein the apparatus is disposed in a Magnetoresistive Random Access Memory (MRAM).

10. The apparatus of claim 1 , wherein the second stage comprises a plurality of logic gates.

11. The apparatus of claim 1 , wherein the first output is smaller than the second output.

12. The apparatus of claim 1 , wherein the second stage further comprises a second plurality of two input port AND gates, each one of the second plurality of two input port AND gates having a first input port respectively connected to one of seven output nodes of the 7:1 decoder and a second input port connected an input bit.

13. The apparatus of claim 12 , wherein inputs to the first plurality of two input port AND gates and the second plurality of two input port AND gates are arranged to reduce standby current for more commonly occurring TRIM codes used in in a sense amplifier (SA) trimming function.

14. A method comprising:
producing, by a first stage, a first output comprising a decoded first input, wherein the first stage comprises a 7:1 decoder;
receiving, by a second stage, the first output from the first stage;
receiving, by a second stage, a second input; and
converting, by the second stage, the first output and the second input from a first code to a second code based on the second input and the first output, wherein the second stage comprises a first plurality of two input port AND gates, each one of the first plurality of two input port AND gates having a first input port respectively connected to one of seven output nodes of the 7:1 decoder and a second input port connected to an inverse of an input bit.

15. The method of claim 14 , wherein the first code comprises Binary.

16. The method of claim 14 , wherein the first code comprises Gray Code.

17. The method of claim 14 , wherein the second code comprises Unary Code.

18. An apparatus configured to:
receive a first input;
produce a first output from the first input by decoding the first input using a 7:1 decoder of a first stage;
receive a second input;
convert the first output and the second input from a first code to a second code based on the second input and the first output at a second stage, wherein the second stage comprises a first plurality of two input port AND gates, each one of the first plurality of two input port AND gates having a first input port respectively connected to one of seven output nodes of the 7:1 decoder and a second input port connected to an inverse of an input bit; and
provide the converted first output and second input to a trimming function of a Sense Amplifier.

19. The apparatus of claim 18 , wherein the first code comprises one of Binary and gray code.

20. The apparatus of claim 18 , wherein the second code comprises Unary Code.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Khwa Win-San
• Noguchi Hiroki
• Lin Ku-Feng

Classifications

• H03M7/16 Primary

  Conversion to or from unit-distance codes, e.g. Gray code, reflected binary code · CPC title

• G11C11/1673

  Reading or sensing circuits or methods · CPC title

• H03K19/20 Primary

  characterised by logic function, e.g. AND, OR, NOR, NOT circuits (H03K19/003 - H03K19/01 take precedence) · CPC title

• G11C11/161 Primary

  details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell · CPC title

• G11C11/1653

  Address circuits or decoders · CPC title