Apparatuses and methods for maintaining a duty cycle error counter

Patent metadata

Field	Value
Publication number	US-10438648-B2
Application number	US-201815868232-A
Country	US
Kind code	B2
Filing date	Jan 11, 2018
Priority date	Jan 11, 2018
Publication date	Oct 8, 2019
Grant date	Oct 8, 2019

Abstract

Apparatuses and methods for maintaining a duty cycle error counter. An example apparatus may a duty cycle detect circuit configured to receive a clock signal and to detect a duty cycle error of the clock signal. The duty cycle detect error includes a counter configured to store a count value indicating the duty cycle error using Gray code. The counter is adjusted in response to detection of non-zero duty cycle error, and the counter is configured to convert the count value from Gray code to binary code as a binary count value. The duty cycle detect circuit is further configured to provide a duty cycle error signal based on the binary count value. The example apparatus further comprising a duty cycle correction circuit configured to adjust a duty cycle of the clock signal based on the duty cycle error signal.

First claim

What is claimed is:

1. An apparatus comprising:
a counter, wherein the counter is configured to:
encode a first value to a second value, wherein the first value is represented by a binary code and the second value is represented by a Gray code,
count up or count down the second value by a specified step to output a third value, wherein the third value is represented by the Gray code, and
decode the third value to a fourth value with masking a part of the fourth value responsive to a control signal, wherein the fourth value is represented by the binary code.

2. The apparatus of claim 1 , wherein to encode the first value to the second value comprises using bitwise XOR logic to compare binary code bit values and Gray code bit values.

3. The apparatus of claim 1 , wherein to decode the third value to the fourth value comprises using bitwise XOR logic to compare binary code bit values.

4. The apparatus of claim 1 , wherein to count up or count down the second value by the specified step to output the third value is in response to a clock signal and based on an UP/DOWN signal, wherein the UP/DOWN signal indicates an increment or decrement of the counter.

5. The apparatus of claim 1 , wherein the specified step is greater than a one bit step.

6. An apparatus comprising:
a duty cycle detect circuit configured to receive a clock signal and to detect a duty cycle error of the clock signal, the duty cycle detect circuit including a counter configured to store a count value indicating the duty cycle error using Gray code, wherein the counter is adjusted in response to detection of non-zero duty cycle error and the counter is further configured to convert the count value from Gray code to binary code as a binary count value, wherein the duty cycle detect circuit is further configured to provide a duty cycle error signal based on the binary count value; and
a duty cycle correction circuit configured to adjust a duty cycle of the clock signal based on the duty cycle error signal.

7. The apparatus of claim 6 , wherein the counter comprises a plurality of bit cells, wherein a bit cell of the plurality of bit cells is configured to adjust a Gray code bit value based on the duty cycle error.

8. The apparatus of claim 7 , wherein the bit cell of the plurality of bit cells comprises a binary-to-Gray code converter to determine a next value of the Gray code bit based on a current binary bit value and a next state binary bit value from a next higher order bit cell of the plurality of bit cells.

9. The apparatus of claim 8 , wherein the binary-to-Gray code converter comprises:
a first XOR logic gate configured to compare a current binary bit value with a next state increment binary bit value from the next higher order bit cell to provide an up Gray code bit;
a second XOR logic gate configured to compare the current binary bit value with a next state decrement binary bit value from the next higher order bit cell to provide a down Gray code bit; and
a multiplexer to select one of the up Gray code bit or the down Gray code bit as the next value of the Gray code bit in response to an UP/DOWN signal, wherein the UP/DOWN signal indicates whether the counter is incremented or decremented.

10. The apparatus of claim 9 , wherein the bit cell of the plurality of bit cells further comprises a flip-flop circuit configured to set the next value of the Gray code as a current value of the Gray code bit in response to a second clock signal, wherein the second clock sitmal controls timing of the adjustment of the counter.

11. The apparatus of claim 8 , wherein the bit cell of the plurality of bit cells comprises a Gray-to-binary code converter to determine the current binary bit value based on the current value of the Gray code bit and a current binary bit value from the next higher order bit cell.

12. The apparatus of claim 11 , wherein the Gray-to-binary code converter to determine the current binary bit value based on the current value of the Gray code bit and the current binary bit value from the next higher order bit cell is via an XOR comparison.

13. The apparatus of claim 7 , wherein a step size adjustment of the counter is based on control signals received at each of the plurality of bit cells.

14. The apparatus of claim 13 , wherein the step size adjustment of the counter comprises at least one of a 2 bit step size, a 4 bit step size, or an 8 bit step size.

15. A method comprising:
receiving a clock signal;
detecting a duty cycle error of the clock signal;
storing a count value indicating the duty cycle error using Gray code;
in response to detecting a non-zero duty cycle error, adjusting the count value by a step size;
converting the count value from Gray code to binary code to provide a binary count value;
providing a duty cycle error signal based on the binary count value; and
adjusting a duty cycle of the clock signal based on the duty cycle error signal.

16. The method of claim 15 , wherein adjusting the count value by the step size comprises, for each bit of the counter, performing bitwise comparisons based on a current binary bit value for a bit of the counter with a next state binary bit value from a next higher order bit of the counter.

17. The method of claim 16 , wherein the bitwise comparisons use XOR logic.

18. The method of claim 15 , wherein converting the count value from Gray code to binary code comprises, for each bit of the counter, performing bitwise comparisons based on a current binary bit value for a bit of the counter with a current binary bit value from a next higher order bit of the counter to provide the binary count value.

19. The method of claim 15 , further comprising setting the step size of the counter to a value greater than a one-bit step.

Assignees

• Micron Technology Inc

Inventors

• Satoh Yasuo
• Gomm Tyler J

Classifications

• H03K23/005

  using minimum change code, e.g. Gray Code · CPC title

• G11C29/028

  with adaption or trimming of parameters · CPC title

• H03K19/21

  EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical · CPC title

• G11C11/4076 Primary

  Timing circuits (for regeneration management G11C11/406) · CPC title

• G11C7/222

  Clock generating, synchronizing or distributing circuits within memory device · CPC title