Buffer controller, memory device, and integrated circuit device

Patent metadata

Field	Value
Publication number	US-10509760-B2
Application number	US-201715855819-A
Country	US
Kind code	B2
Filing date	Dec 27, 2017
Priority date	Jul 12, 2017
Publication date	Dec 17, 2019
Grant date	Dec 17, 2019

Abstract

A buffer controller includes a pointer generator, a code converter, a synchronizer, a code restorer, and a comparator. The pointer generator operates according to a first clock signal, and generates a first pointer by encoding a first address of a buffer with a first code. The code converter generates a first transmission pointer by converting the first pointer with a second code or a third code according to an amount of data stored in or read from the first address. The synchronizer synchronizes the first transmission pointer with a second clock signal. The code restorer generates a first comparison pointer by restoring the first transmission pointer, synchronized with the second clock signal, with the first code. The comparator compares the first comparison pointer with a second pointer. The second pointer defines a second address of the buffer with the first code.

First claim

What is claimed is:

1. A buffer controller, comprising:
a pointer generator configured to operate according to a first clock signal, and generate a first pointer by encoding a first address of a buffer with a first code;
a code converter configured to generate a first transmission pointer by converting the first pointer with one of a second code and a third code, different from the first code, selected according to an amount of data stored in the first address or read from the first address;
a synchronizer configured to synchronize the first transmission pointer with a second clock signal different from the first clock signal;
a code restorer configured to generate a first comparison pointer by restoring the first transmission pointer, synchronized with the second clock signal, with the first code; and
a comparator configured to compare the first comparison pointer with a second pointer, the second pointer defining a second address of the buffer with the first code.

2. The buffer controller of claim 1 , wherein the synchronizer and the code restorer operate according to the second clock signal.

3. The buffer controller of claim 1 , wherein the comparator compares the first comparison pointer with the second pointer to detect at least one of an overflow and an underflow of the buffer.

4. The buffer controller of claim 1 , wherein the first code is a binary code, the second code is a gray code generated from the first code, the third code is a code generated by combining a portion of the first code with a portion of the second code, and
each of the first code, the second code, and the third code includes N number of bits, where N is a natural number greater than 2.

5. The buffer controller of claim 4 , wherein, when an amount of data stored in the first address or read from the first address during one period of the first clock signal is a first amount, the code converter converts the first pointer with the second code based on the amount of data being the first amount.

6. The buffer controller of claim 5 , wherein, when the amount of data stored in the first address or read from the first address during one period of the first clock signal is a second amount, larger than the first amount, the code converter converts the first pointer with the third code based on the amount of data being the second amount.

7. The buffer controller of claim 4 , wherein
n is a natural number less than N,
n number of upper bits of the third code have the same value with n number of upper bits of the second code, and
N−n number of lower bits of the third code have the same value with the N−n number of lower bits of the first code.

8. The buffer controller of claim 7 , wherein the code converter includes:
a first code generator configured to convert the first code into the second code;
a second code generator configured to generate the third code by combining a portion of the first code with a portion of the second code; and
a code selector configured to control the code converter to output one of the second code and the third code, based on the amount of data stored in the first address or read from the first address during one period of the first clock signal.

9. The buffer controller of claim 8 , wherein the first code generator includes N−1 number of exclusive-OR (XOR) gates.

10. The buffer controller of claim 7 , wherein n is determined according to a size of a skip symbol added to the data or deleted from the data.

11. The buffer controller of claim 7 , wherein the code converter includes a multiplexer that selects one of N−n number of lower bits of the first code and N−n number of lower bits of the second code.

12. The buffer controller of claim 1 , wherein the synchronizer includes a plurality of flip-flops connected to each other in series, and the plurality of flip-flops operate according to the second clock signal.

13. A memory device, comprising:
a buffer;
a first pointer generator configured to operate according to a first clock signal, and generate a first pointer by encoding a first address of the buffer with a first code;
a write circuit configured to store first data in a storage space of the buffer corresponding to the first address;
a second pointer generator configured to operate according to a second clock signal different from the first clock signal, and generate a second pointer by encoding a second address of the buffer with the first code;
a read circuit configured to read second data stored in a storage space of the buffer corresponding to the second address; and
a pointer synchronizer configured to synchronize the first pointer with the second clock signal after converting the first pointer with a transmission code different from the first code, and compare the first pointer with the second pointer by restoring the first pointer, synchronized with the second clock signal, with the first code,
wherein the transmission code is a code in which only a single bit is changed in each period of the first clock signal.

14. The memory device of claim 13 , wherein the pointer synchronizer synchronizes the second pointer with the first clock signal after converting the second pointer with the transmission code, and compares the second pointer with the first pointer by restoring the second pointer, synchronized with the first clock signal, with the first code.

15. The memory device of claim 13 , wherein the transmission code is one of a second code and a third code, different from the first code, selected according to an amount of data stored in the first address or read from the first address, and the third code is generated by combining a portion of bits of the first code with a portion of bits of the second code.

16. The memory device of claim 15 , wherein the first code is a binary code, and the second code is a gray code.

17. The memory device of claim 16 , wherein the pointer synchronizer generates the third code by combining a portion of upper bits of the second code with a portion of lower bits of the first code.

18. An integrated circuit device, comprising:
a first circuit configured to operate according to a first clock signal;
a second circuit configured to operate according to a second clock signal different from the first clock signal; and
a memory device configured to store first data in a first address according to the first clock signal, and to output second data stored in a second address to the second circuit according to the second clock signal,
wherein the first data is input by the first circuit,
the memory device compares a first pointer that indicates the first address with a second pointer that indicates the second address, by synchronizing the first pointer with the second clock signal after encoding the first pointer with a transmission code, and compares the second pointer with the first pointer by synchronizing the second pointer with the first clock signal after encoding the second pointer with the transmission code, and
the transmission code is a code in which only a single bit is changed regardless of an amount of the first data and an amount of the second data, the first data is synchronized with the first clock signal and stored in the memory device, and the second data is synchronized with the second clock signal and output by the memory device.

19. The integrated circuit device of claim 18 , wherein the transmission code is one of a gray code, or a code in which a gray code and a binary code are combined with each other.

20. The integrated circuit device of claim 18

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee June Hee
• Shin Min Bo

Classifications

• G06F2205/126

  Monitoring of intermediate fill level, i.e. with additional means for monitoring the fill level, e.g. half full flag, almost empty flag · CPC title

• G11C7/222

  Clock generating, synchronizing or distributing circuits within memory device · CPC title

• G11C8/04

  using a sequential addressing device, e.g. shift register, counter · CPC title

• G11C2207/007

  Register arrays · CPC title

• G06F13/1673

  using buffers · CPC title