Semiconductor device

Patent metadata

Field	Value
Publication number	US-11961806-B2
Application number	US-202117352503-A
Country	US
Kind code	B2
Filing date	Jun 21, 2021
Priority date	Dec 1, 2020
Publication date	Apr 16, 2024
Grant date	Apr 16, 2024

Abstract

A semiconductor device may include a substrate including a first region and a second region and a first active pattern on the first region. The first active pattern may include a pair of first source/drain patterns and a first channel pattern therebetween, and the first channel pattern may include a plurality of first semiconductor patterns stacked on the substrate. The semiconductor device may further include a first gate electrode, which is provided on the first channel patterns, and a supporting pattern, which is provided on side surfaces of the plurality of first semiconductor patterns to connect the side surfaces of the plurality of first semiconductor patterns to each other.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a substrate including a first region and a second region;
a first active pattern on the first region, the first active pattern comprising a pair of first source/drain patterns and a first channel pattern therebetween, the first channel pattern comprising a plurality of first semiconductor patterns stacked on the substrate;
a first gate electrode provided on the first channel pattern; and
a supporting pattern provided on side surfaces of the plurality of first semiconductor patterns to connect the side surfaces of the plurality of first semiconductor patterns to each other.

2. The semiconductor device of claim 1 ,
wherein the supporting pattern comprises the same material as the plurality of first semiconductor patterns.

3. The semiconductor device of claim 1 ,
wherein a length of the first channel pattern has a value between 100 nm and 300 nm, and
wherein a width of the supporting pattern has a value between 5 nm and 30 nm.

4. The semiconductor device of claim 1 ,
wherein a thickness of the supporting pattern is smaller than a thickness of each of the first semiconductor patterns.

5. The semiconductor device of claim 1 ,
wherein a thickness of the supporting pattern has a value between 2 nm and 3 nm.

6. The semiconductor device of claim 1 ,
wherein the supporting pattern is extended to be in contact with a top surface of the uppermost one of the first semiconductor patterns.

7. The semiconductor device of claim 1 , further comprising:
a first gate insulating layer between the first channel pattern and the first gate electrode,
wherein the first gate insulating layer is in contact with the supporting pattern.

8. The semiconductor device of claim 1 , further comprising:
a second active pattern and a second gate electrode provided on the second region,
wherein the second active pattern comprises a pair of second source/drain patterns and a second channel pattern therebetween,
wherein the second channel pattern comprises a plurality of second semiconductor patterns stacked on the substrate,
wherein the second gate electrode is provided on the second channel pattern, and
wherein a length of the first channel pattern is larger than a length of the second channel pattern.

9. A semiconductor device, comprising:
a substrate including a first region and a second region;
a first active pattern on the first region, the first active pattern comprising a pair of first source/drain patterns and a first channel pattern therebetween, the first channel pattern comprising a plurality of first semiconductor patterns stacked on the substrate;
a second active pattern on the second region, the second active pattern comprising a pair of second source/drain patterns and a second channel pattern therebetween, the second channel pattern comprising a plurality of second semiconductor patterns stacked on the substrate;
a supporting pattern configured to fasten the plurality of first semiconductor patterns and having an arch-shaped section; and
a first gate electrode and a second gate electrode provided on the first and second channel patterns, respectively,
wherein a length of the first channel pattern is larger than a length of the second channel pattern, and
wherein the plurality of first semiconductor patterns include a first material and the supporting pattern includes the first material.

10. The semiconductor device of claim 9 ,
wherein the supporting pattern has a first side surface and a second side surface, which are opposite to each other, and
wherein the first side surface and the second side surface are spaced apart from each other with the plurality of first semiconductor patterns interposed therebetween.

11. The semiconductor device of claim 9 ,
wherein the supporting pattern and the plurality of first semiconductor patterns are connected to form a single object.

12. The semiconductor device of claim 9 ,
wherein the first gate electrode covers the supporting pattern, and
wherein the semiconductor device further comprises a gate insulating layer between the first gate electrode and the supporting pattern.

13. The semiconductor device of claim 9 ,
wherein the plurality of first semiconductor patterns and the supporting pattern have the same crystal direction.

14. The semiconductor device of claim 9 ,
wherein the supporting pattern comprises amorphous silicon.

15. A semiconductor device, comprising:
a substrate including a first region and a second region;
a device isolation layer defining a first active region on the first region and a second active region on the second region;
a pair of first source/drain patterns and a pair of second source/drain patterns on the first active region and the second active region, respectively;
a first channel pattern between the pair of first source/drain patterns;
a second channel pattern between the pair of second source/drain patterns, each of the first and second channel patterns comprising first to third semiconductor patterns sequentially stacked on the substrate;
a first gate electrode and a second gate electrode on the first channel pattern and the second channel pattern, respectively;
a first gate insulating layer between the first channel pattern and the first gate electrode;
a second gate insulating layer between the second channel pattern and the second gate electrode;
a pair of gate spacers provided at opposite sides of each of the first and second gate electrodes;
a gate capping pattern on a top surface of each of the first and second gate electrodes;
a pair of first active contacts electrically connected to the pair of first source/drain patterns;
a pair of second active contacts electrically connected to the pair of second source/drain patterns;
first and second gate contacts electrically connected to the first and second gate electrodes;
a first metal layer on the pair of first active contacts, the pair of second active contacts, and the first and second gate contacts, the first metal layer comprising first interconnection lines electrically connected to the pair of first active contacts, the pair of second active contacts, and the first and second gate contacts;
a second metal layer on the first metal layer; and
a first supporting pattern, which is provided on side surfaces of the first to third semiconductor patterns of the first channel pattern and is in contact with the first to third semiconductor patterns thereof,
wherein the first supporting pattern comprises:
a first vertical portion and a second vertical portion, which are provided on the first active region and are extended from a top surface of the device isolation layer to a top surface of the third semiconductor pattern, and
a connecting portion, which is in contact with the top surface of the third semiconductor pattern and connects the first vertical portion to the second vertical portion,

wherein the first vertical portion and the second vertical portion are spaced apart from each other with the first to third semiconductor pattern of the first channel pattern interposed therebetween.

16. The semiconductor device of claim 15 ,
wherein a thickness of the first supporting pattern is smaller than a thickness of each of the first to third semiconductor patterns of the first channel pattern.

17. The semiconductor device of claim 16 ,
wherein the first supporting pattern and the first to third semiconductor patterns of the first channel pattern are connected to form a single object.

18. The semiconductor device of

Assignees

• Samsung Electronics Co Ltd

Inventors

• Park Noh Yeong
• Park Beomjin
• Bae Dong Il
• Baek Sangwon
• Song Hyun-Seung

Classifications

• H10P14/3452

  Microstructure · CPC title

• H10W42/121 Primary

  protecting against mechanical damage (H10W76/00, H10W74/00 take precedence) · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D30/6735

  having gates fully surrounding the channels, e.g. gate-all-around · CPC title

• H10D62/121

  oriented parallel to substrates · CPC title