Dual metal gate structure having portions of metal gate layers in contact with a gate dielectric

Patent metadata

Field	Value
Publication number	US-11955532-B2
Application number	US-202017080713-A
Country	US
Kind code	B2
Filing date	Oct 26, 2020
Priority date	Nov 30, 2017
Publication date	Apr 9, 2024
Grant date	Apr 9, 2024

Abstract

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a semiconductor substrate comprising an N well region having a semiconductor fin protruding therefrom. A trench isolation layer is on the semiconductor substrate around the semiconductor fin, wherein the semiconductor fin extends above the trench isolation layer. A gate dielectric layer is over the semiconductor fin. A conductive layer is over the gate dielectric layer over the semiconductor fin, the conductive layer comprising titanium, nitrogen and oxygen. A P-type metal gate layer is over the conductive layer over the semiconductor fin.

First claim

What is claimed is:

1. An integrated circuit structure, comprising:
an inter-layer dielectric layer having a trench therein, the trench having a sidewall;
a semiconductor substrate having a semiconductor fin protruding therefrom and extending into the trench in the inter-layer dielectric layer;
a trench isolation layer on the semiconductor substrate around a lower portion of the semiconductor fin, wherein an upper portion of the semiconductor fin extends above the trench isolation layer;
a gate dielectric over the upper portion of the semiconductor fin, the gate dielectric having a portion laterally spaced apart from the semiconductor fin and along the sidewall of the trench in the inter-layer dielectric layer;
a conductive layer over the gate dielectric, the conductive layer comprising titanium, nitrogen and oxygen, and a portion of the conductive layer in contact with the portion of the gate dielectric laterally spaced apart from the semiconductor fin;
a P-type metal gate layer over the conductive layer, the P-type metal gate layer having an uppermost surface above an uppermost surface of the conductive layer, and a portion of the P-type metal gate layer in contact with the portion of the gate dielectric laterally spaced apart from the semiconductor fin;
an N-type metal gate layer over the P-type metal gate layer, a portion of the N-type metal gate layer in contact with the portion of the gate dielectric laterally spaced apart from the semiconductor fin; and
a conductive fill over the N-type metal gate layer.

2. The integrated circuit structure of claim 1 , wherein the P-type metal gate layer comprises titanium and nitrogen.

3. The integrated circuit structure of claim 1 , wherein the N-type metal gate layer comprises titanium and aluminum.

4. The integrated circuit structure of claim 1 , wherein the conductive fill comprises 95 or greater atomic percent tungsten.

5. The integrated circuit structure of claim 4 , wherein the conductive fill further comprises 0.1 to 2 atomic percent fluorine.

6. The integrated circuit structure of claim 1 , wherein the gate dielectric comprises a layer comprising hafnium and oxygen.

7. The integrated circuit structure of claim 6 , wherein the gate dielectric further comprises an oxide layer between the upper portion of the semiconductor fin and the layer comprising hafnium and oxygen, the oxide layer comprising silicon and oxygen.

8. The integrated circuit structure of claim 1 , wherein the conductive layer is directly on the gate dielectric, the P-type metal gate layer is directly on the conductive layer, the N-type metal gate layer is directly on the P-type metal gate layer, and the conductive fill is directly on the N-type metal gate layer.

9. The integrated circuit structure of claim 8 , wherein the P-type metal gate layer comprises titanium and nitrogen, wherein the N-type metal gate layer comprises titanium and aluminum, and wherein the conductive fill comprises 95 or greater atomic percent tungsten.

10. The integrated circuit structure of claim 9 , wherein the conductive fill further comprises 0.1 to 2 atomic percent fluorine.

11. The integrated circuit structure of claim 1 , wherein the semiconductor substrate is a silicon semiconductor substrate.

12. A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, comprising:
an inter-layer dielectric layer having a trench therein, the trench having a sidewall;
a semiconductor substrate having a semiconductor fin protruding therefrom and extending into the trench in the inter-layer dielectric layer;
a trench isolation layer on the semiconductor substrate around a lower portion of the semiconductor fin, wherein an upper portion of the semiconductor fin extends above the trench isolation layer;
a gate dielectric over the upper portion of the semiconductor fin, the gate dielectric having a portion laterally spaced apart from the semiconductor fin and along the sidewall of the trench in the inter-layer dielectric layer;
a conductive layer over the gate dielectric, the conductive layer comprising titanium, nitrogen and oxygen, and a portion of the conductive layer in contact with the portion of the gate dielectric laterally spaced apart from the semiconductor fin;
a P-type metal gate layer over the conductive layer, the P-type metal gate layer having an uppermost surface above an uppermost surface of the conductive layer, and a portion of the P-type metal gate layer in contact with the portion of the gate dielectric laterally spaced apart from the semiconductor fin;
an N-type metal gate layer over the P-type metal gate layer, a portion of the N-type metal gate layer in contact with the portion of the gate dielectric laterally spaced apart from the semiconductor fin; and
a conductive fill over the N-type metal gate layer.

13. The computing device of claim 12 , further comprising:
a memory coupled to the board.

14. The computing device of claim 12 , further comprising:
a communication chip coupled to the board.

15. The computing device of claim 12 , further comprising:
a camera coupled to the board.

16. The computing device of claim 12 , further comprising:
a battery coupled to the board.

17. The computing device of claim 12 , further comprising:
an antenna coupled to the board.

18. The computing device of claim 12 , wherein the component is a packaged integrated circuit die.

19. The computing device of claim 12 , wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.

20. The computing device of claim 12 , wherein the computing device is selected from the group consisting of a mobile phone, a laptop, a desk top computer, a server, and a set-top box.

Assignees

• Intel Corp

Inventors

• Leib Jeffrey S
• Hu Jenny
• Dasgupta Anindya
• Hattendorf Michael L
• Auth Christopher P

Classifications

• H10W20/4437

  the principal metal being a transition metal · CPC title

• H10W20/0693

  by forming self-aligned vias · CPC title

• H10W72/30

  Die-attach connectors · CPC title

• H10W72/20

  Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps · CPC title

• H10W72/851

  Dispositions of multiple connectors or interconnections · CPC title