Temperature control element utilized in device die packages

Patent metadata

Field	Value
Publication number	US-11955406-B2
Application number	US-202217570647-A
Country	US
Kind code	B2
Filing date	Jan 7, 2022
Priority date	Nov 19, 2021
Publication date	Apr 9, 2024
Grant date	Apr 9, 2024

Abstract

An IC die includes a temperature control element suitable for three-dimensional IC package with enhanced thermal control and management. The temperature control element may assist temperature control of the IC die when in operation. In one example, the temperature control element may have a plurality of thermal dissipating features disposed on a first surface of the IC die to efficiently control and dissipate the thermal energy from the IC die when in operation. A second surface opposite to the first surface of the IC die may include a plurality of devices, such as semiconductors transistors, devices, electrical components, circuits, or the like, that may generate thermal energy when in operation. The temperature control element may provide an IC die with high efficiency of heat dissipation that is suitable for 3D IC package structures and requirements.

First claim

The invention claimed is:

1. An integrated circuit (“IC”) package, comprising:
an IC die disposed on a printed circuit board (“PCB”), and
a temperature control element encasing the IC die, wherein the temperature control element comprises:
a plurality of thermal dissipating features disposed on a first surface of the IC die;
a manifold disposed on the PCB encasing the plurality of thermal dissipating features disposed on the IC die; and
a spacer disposed between the plurality of thermal dissipating features and the manifold,
wherein the plurality of thermal dissipating features comprises a metallic pin fin disposed on a solder bump.

2. The IC package of claim 1 , wherein the metallic pin fin is manufactured from a material selected from copper, aluminum, tungsten, gold, silver, combinations thereof or alloys thereof.

3. The IC package of claim 1 , wherein the plurality of thermal dissipating features is arranged in one or more arrays or matrices.

4. The IC package of claim 1 , further comprising:
a sealing member disposed between the manifold and the IC die.

5. The IC package of claim 1 , wherein the manifold comprises:
a first sidewall;
a second sidewall; and
a ceiling disposed between the first and the second sidewall, defining a central cavity that allows the IC die to be encased therein.

6. The IC package of claim 5 , further comprising:
a plenum defined in a center portion of the ceiling.

7. The IC package of claim 6 , wherein the plenum allows fluid to flow therethrough from an inlet to an outlet of the plenum.

8. The IC package of claim 1 , wherein the plurality of thermal dissipating features has a circular configuration, a rectangular configuration, or a longitudinal structure.

9. The IC package of claim 1 , wherein the thermal dissipating features have different aspect ratios.

10. The IC package of claim 1 , further comprises:
a metallization layer disposed between the plurality of thermal dissipating features and the IC die.

11. The IC package of claim 1 , wherein the thermal dissipating features are divided into a first and a second zone disposed on the IC die, wherein the first zone has a higher number of the thermal dissipating features than the second zone.

12. The IC package of claim 1 , wherein the plurality of the thermal dissipating features has a top surface spaced apart from the manifold.

13. The IC package of claim 1 , wherein the plurality of the thermal dissipating features has a top surface in direct contact with the manifold.

14. The IC package of claim 1 , wherein the IC die has a second surface opposite to the first surface, wherein device structures are formed on the second surface of the IC die.

15. A temperature control element, comprising:
a plurality of thermal dissipating features configured to be disposed on a surface of an integrated circuit (“IC”) die, wherein the plurality of thermal dissipating features further comprises:

a metallic pin fin disposed on a solder bump;
a manifold having a plenum configured to encase the plurality of thermal dissipating features disposed on the IC die; and
a spacer disposed between the plurality of thermal dissipating features and the manifold.

16. The temperature control element of claim 15 , wherein the plenum is configured to receive fluid to control temperature of the IC die when in operation.

17. A method for manufacturing a temperature control element in an integrated circuit (“IC”) package comprising an IC die, the method comprising:
disposing a plurality of thermal dissipating features on an IC die disposed on a printed circuit board (“PCB”), wherein the plurality of thermal dissipating features further comprises: a metallic pin fin disposed on a solder bump;
placing a manifold on the PCB to encase the IC die therein while maintaining the plurality of thermal dissipating features located in a plenum defined in the manifold;
disposing a spacer between the plurality of thermal dissipating features and the manifold; and
supplying a fluid into the plenum to regulate a thermal energy transmitted from the IC die.

Assignees

• Google Llc

Inventors

• Wang Yingying
• Samadiani Emad
• Iyengar Madhusudan K
• Jain Padam
• Wei Xiaojin
• Kang Teckgyu
• Udhayakumar Sudharshan Sugavanesh
• Tang Yingshi

Classifications

• H10W90/731

  of die-attach connectors · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/877

  Bump connectors and die-attach connectors · CPC title

• H10W72/344

  relative to underlying supporting features, e.g. bond pads, RDLs or vias · CPC title

• H10W74/01

  Manufacture or treatment · CPC title