Mating backplane for high speed, high density electrical connector

Patent metadata

Field	Value
Publication number	US-11950356-B2
Application number	US-202218079956-A
Country	US
Kind code	B2
Filing date	Dec 13, 2022
Priority date	Nov 21, 2014
Publication date	Apr 2, 2024
Grant date	Apr 2, 2024

Abstract

A printed circuit board includes a plurality of layers including attachment layers and routing layers; and via patterns formed in the plurality of layers, each of the via patterns including first and second signal vias forming a differential signal pair, the first and second signal vias extending through at least the attachment layers; ground vias extending through at least the attachment layers, the ground vias including ground conductors; and shadow vias located adjacent to each of the first and second signal vias, wherein the shadow vias are free of conductive material in the attachment layers. The printed circuit board may further include slot vias extending through the attachment layers and located between via patterns.

First claim

What is claimed is:

1. A printed circuit board comprising:
a plurality of layers including conductive layers separated by dielectric layers; and
via patterns formed in one or more of the plurality of layers, each of the via patterns comprising:
first and second signal vias connecting to respective signal traces on one or more of the plurality of layers;
ground vias extending through at least some layers of the plurality of layers; and
at least one shadow via extending through at least some layers of the plurality of layers, wherein the at least one shadow via is plated or filled with a conductive material and wherein the at least one shadow via is located on a first line that passes through one of the first and second signal vias, the first line being perpendicular to a second line that passes through the first and second signal vias.

2. The printed circuit board as defined in claim 1 , wherein the at least one shadow via is located in proximity to one of the first and second signal vias.

3. The printed circuit board as defined in claim 1 , wherein the at least one shadow via comprises first and second shadow vias located in proximity to the first signal via and third and fourth shadow vias located in proximity to the second signal via.

4. The printed circuit board as defined in claim 3 , wherein the first and second shadow vias are located on opposite sides of the first signal via and the third and fourth shadow vias are located on opposite sides of the second signal via.

5. The printed circuit board as defined in claim 1 , wherein the at least one shadow via extends to a predetermined depth in the plurality of layers.

6. The printed circuit board as defined in claim 1 , wherein the at least one shadow via extends through the plurality of layers.

7. The printed circuit board as defined in claim 1 , wherein the at least one shadow via is in electrical contact with one or more of the conductive layers.

8. The printed circuit board as defined in claim 1 , wherein the at least one shadow via is located in proximity to one of the ground vias.

9. The printed circuit board as defined in claim 1 , wherein the at least one shadow via is smaller in diameter than the first and second signal vias.

10. The printed circuit board as defined in claim 1 , wherein the at least one shadow via is smaller in diameter than the ground vias.

11. A printed circuit board comprising:
a plurality of layers including conductive layers separated by dielectric layers;
first and second signal vias forming a differential signal pair, the first and second signal vias extending through one or more of the plurality of layers; and
at least one shadow via parallel to and spaced apart from one of the first and second signal vias, wherein the at least one shadow via is plated or filled with a conductive material, wherein at least one of the conductive layers of the plurality of layers is removed in an area around the first and second signal vias to form an antipad, and wherein the at least one shadow via is located, at least partially, within the antipad.

12. The printed circuit board as defined in claim 11 , wherein the at least one shadow via includes shadow vias located on opposite sides of the first and second signal vias.

13. The printed circuit board as defined in claim 11 , wherein the at least one shadow via has a smaller diameter than the first and second signal vias.

14. The printed circuit board as defined in claim 11 , wherein the at least one shadow via comprises first and second shadow vias located in proximity to the first signal via and third and fourth shadow vias located in proximity to the second signal via.

15. The printed circuit board as defined in claim 11 , wherein the at least one shadow via is in electrical contact with one or more of the conductive layers.

16. A printed circuit board comprising:
a plurality of layers including conductive layers separated by dielectric layers; and
a connector footprint comprising:
first and second signal vias forming a differential signal pair, the first and second signal vias extending through one or more of the plurality of layers; and
at least one shadow via associated with one of the first and second signal vias and extending to a predetermined depth in the plurality of layers, wherein the at least one shadow via is located on a first line that passes through one of the first and second signal vias, the first line being perpendicular to a second line that passes through the first and second signal vias.

17. The printed circuit board as defined in claim 16 , wherein the at least one shadow via comprises first and second shadow vias located in proximity to the first signal via and third and fourth shadow vias located in proximity to the second signal via.

18. The printed circuit board as defined in claim 16 , wherein the at least one shadow via is smaller in diameter than the first and second signal vias.

Assignees

• Amphenol Corp

Inventors

• Gailus Mark W
• Cartier Jr Marc B
• Sivarajan Vysakh
• Levine David

Classifications

• H05K1/0222 Primary

  for shielding around a single via or around a group of vias, e.g. coaxial vias or vias surrounded by a grounded via fence · CPC title

• H01R43/205 Primary

  with a panel or printed circuit board · CPC title

• H05K1/0216

  Reduction of cross-talk, noise or electromagnetic interference (grounding H05K1/0215) · CPC title

• H05K1/0219 Primary

  Printed shielding conductors for shielding around or between signal conductors, e.g. coplanar or coaxial printed shielding conductors · CPC title

• H05K1/025

  Impedance arrangements, e.g. impedance matching, reduction of parasitic impedance (H05K1/024 and H05K1/0243 take precedence; for semiconductor devices H10W44/20) · CPC title