Calibration with feedback sensing

Patent metadata

Field	Value
Publication number	US-11942959-B2
Application number	US-202117487199-A
Country	US
Kind code	B2
Filing date	Sep 28, 2021
Priority date	Sep 28, 2021
Publication date	Mar 26, 2024
Grant date	Mar 26, 2024

Abstract

A calibration circuit, including: a signal generator circuit configured to generate a modulated analog input signal, which is based on a digital input word that is modulated; an Analog-to-Digital Converter (ADC) configured to convert an analog reference signal to a digital calibration word, wherein the analog reference signal is a low-pass-filtered version of the analog input signal generated by the signal generator circuit; and a feedback circuit configured to output the digital input word by adjusting the digital calibration word depending on a digital feedback signal, which is based on a modulated version of the analog reference signal, wherein the signal generator circuit, the ADC, and the feedback circuit are provided on a same chip.

First claim

The invention claimed is:

1. A calibration circuit for calibrating an Analog-to-Digital Converter (ADC), comprising:
a processor configured to generate a digital input word during a calibration;
a signal generator circuit connected to the processor, the signal generator circuit being configured to generate a modulated analog input signal, which is based on the digital input word that is modulated;
the ADC, which is configured to convert an analog reference signal to a digital calibration word, wherein the analog reference signal is a low-pass-filtered version of the analog input signal generated by the signal generator circuit; and
a feedback circuit configured to output a digital feedback signal to the processor, the digital feedback signal being based on a modulated version of the analog reference signal, and
wherein the signal generator circuit, the ADC, and the feedback circuit are provided on a same chip, and
wherein the processor is further configured to, after the calibration, generate using the ADC the digital input word based on an analog signal while compensating for non-linear errors in the ADC using the digital calibration word.

2. The calibration circuit of claim 1 , wherein the feedback circuit comprises:
an analog modulator configured to modulate the analog reference signal into the modulated analog reference signal.

3. The calibration circuit of claim 2 , wherein the feedback circuit further comprises:
a digital Low Pass Filter (LPF), coupled between the analog modulator and the processor, and configured to low-pass-filter the modulated analog reference signal to output the digital feedback signal.

4. The calibration circuit of claim 3 , wherein the digital LPF is a cascaded integrator-comb (CIC) filter or a finite impulse response (FIR) filter.

5. The calibration circuit of claim 2 , wherein the signal generator circuit comprises:
a digital modulator configured to modulate the digital input word to output the analog input signal.

6. The calibration circuit of claim 5 , wherein the signal generator circuit further comprises:
a driver, coupled to the digital modulator, and configured to drive the analog input signal from the digital modulator to output the modulated analog input signal.

7. The calibration circuit of claim 5 , wherein the digital modulator is a High Speed Pulse Density Modulator (HSPDM), and the analog modulator is an Enhanced Delta-Sigma (EDS) ADC.

8. The calibration circuit of claim 5 , wherein the digital modulator and analog modulator are of corresponding types.

9. The calibration circuit of claim 8 , wherein the digital modulator is a delta-sigma Digital-to-Analog Converter (DAC) and the analog modulator is a delta-sigma ADC, or the digital modulator is a pulse frequency digital modulator and the analog modulator is a pulse frequency analog modulator, or the digital modulator is a pulse width digital modulator and the analog modulator is a pulse width analog modulator, or the digital modulator is a pulse code digital modulator and the analog modulator is a pulse code analog modulator.

10. The calibration circuit of claim 1 , wherein the ADC is a sample-and-hold ADC, a successive approximation register (SAR) ADC, or a pipelined ADC.

11. The calibration circuit of claim 1 , wherein the digital calibration word is for measuring differential non-linearity (DNL) or integrated non-linearity (INL) performance of the ADC.

12. A calibration circuit for calibrating an Analog-to-Digital Converter (ADC), comprising:
a processor configured to generate a digital input word;
a signal generator circuit connected to the processor, the signal generator circuit being configured to generate an analog input signal based on the digital input word;
the ADC, which is configured to convert an analog reference signal to a digital calibration word, wherein the analog reference signal is a low-pass-filtered version of the analog input signal generated by the signal generator circuit; and
a feedback circuit configured to output a digital feedback signal to the processor, wherein the digital feedback signal is based on the analog input signal, and
wherein the signal generator circuit, the ADC, and the feedback circuit are provided on a same chip, and
wherein the processor is configured to, after the calibration, generate using the ADC the digital input word based on an analog signal while compensating for non-linear errors in the ADC using the digital calibration word.

13. The calibration circuit of claim 12 , wherein the feedback circuit further comprises:
a Low Pass Filter (LPF), coupled to the processor, and configured to low-pass-filter the analog input signal to output the analog digital feedback signal.

14. The calibration circuit of claim 12 , wherein the signal generator circuit comprises:
a digital modulator configured to modulate the digital input word to output the analog input signal.

15. The calibration circuit of claim 14 , wherein the signal generator circuit further comprises:
a driver, coupled to the digital modulator, and configured to drive the analog input signal output by the digital modulator to output the analog input signal.

16. The calibration circuit of claim 14 , wherein the digital modulator is a High Speed Pulse Density Modulator (HSPDM).

17. The calibration circuit of claim 14 , wherein the digital modulator is a delta-sigma Digital-to-Analog Converter (DAC), a pulse frequency digital modulator, a pulse width digital modulator, or a pulse code digital modulator.

18. The calibration circuit of claim 12 , wherein the ADC is a sample-and-hold ADC, a successive approximation register (SAR) ADC, or a pipelined ADC.

19. The calibration circuit of claim 12 , wherein the digital calibration word is for measuring differential non-linearity (DNL) or integrated non-linearity (INL) performance of the ADC.

20. The calibration circuit of claim 1 , wherein the chip is a chip of a microcontroller.

21. The calibration circuit of claim 12 , wherein the chip is a chip of a microcontroller.

22. The calibration circuit of claim 1 , wherein the processor is software or firmware based.

23. The calibration circuit of claim 12 , wherein the processor is software or firmware based.

Assignees

• Infineon Technologies Ag

Inventors

• Jefremow Mihail
• Koeck Stefan
• Mueller-Eschenbach Ralph
• Schaefer Juergen
• Voigtlaender Arndt
• Zipperstein David

Classifications

• H03M1/1014 Primary

  at one point of the transfer characteristic, i.e. by adjusting a single reference value, e.g. bias or gain error (gain setting for range control H03M1/18) · CPC title

• H03M1/0626

  by filtering · CPC title

• H03M3/464

  Details of the digital/analogue conversion in the feedback path · CPC title

• H03M1/109 Primary

  for DC performance, i.e. static testing (H03M1/1085 takes precedence) · CPC title

• H03M3/50

  Digital/analogue converters using delta-sigma modulation as an intermediate step (digital delta-sigma modulators per se H03M7/3004) · CPC title