Digital class-D amplifier with analog feedback

Patent metadata

Field	Value
Publication number	US-9344046-B2
Application number	US-201314144262-A
Country	US
Kind code	B2
Filing date	Dec 30, 2013
Priority date	Dec 20, 2013
Publication date	May 17, 2016
Grant date	May 17, 2016

Abstract

Methods, systems, and apparatuses for detecting and suppressing analog error in an output stage of a digital class-D amplifier are described. In embodiments, the digital class-D amplifier includes a PWM stage, an output stage, and a feedback circuit. The PWM stage receives the signal difference between an input digital signal and a feedback digital signal, generates a digital pulse-width modulated (PWM) signal based thereon, and provides the digital PWM signal as a first component of the digital feedback signal. The output stage receives the digital PWM signal and generates an analog output signal for driving a load responsive to the digital PWM signal. The feedback circuit combines an analog representation of the PWM signal and the analog output signal to generate a second component of the digital feedback signal.

First claim

What is claimed is:

1. A class-D amplifier, comprising:
a first combiner operable to combine a digital input signal and a digital feedback signal to generate a first combined signal;
a digital loop operable to receive the first combined signal and to generate a digital pulse-width modulated (PWM) signal based thereon and to provide the digital PWM signal as a first component of the digital feedback signal and as an input to a feedback circuit;
an output stage operable to receive the digital PWM signal and to generate an analog output signal for driving a load responsive to the digital PWM signal; and
the feedback circuit comprising
a digital to analog converter (DAC) operable to convert the digital PWM signal to an analog PWM signal,
a second combiner operable to combine the analog PWM signal and the analog output signal to generate a second combined signal, and
an analog to digital converter (ADC) operable to convert the second combined signal to a digital form to generate a second component of the digital feedback signal.

2. The class-D amplifier of claim 1 , wherein the first combiner comprises: a subtractor operable to subtract the digital feedback signal from the digital input signal.

3. The class-D amplifier of claim 1 , wherein the DAC comprises an inverter.

4. The class-D amplifier of claim 1 , wherein the second combiner comprises a first resistor, a second resistor, a third resistor, and an operational amplifier,
the first resistor having a first terminal coupled to an output of the output stage and a second terminal coupled to an input of the operational amplifier,
the second resistor having a first terminal coupled to the output of the DAC and a second terminal coupled to the input of the operational amplifier,
the third resistor having a first terminal coupled to an output of the operational amplifier and a second terminal coupled to the input of the operational amplifier.

5. The class-D amplifier of claim 1 , wherein a reference voltage of the DAC and a reference voltage of the ADC are equal.

6. The class-D amplifier of claim 1 , wherein the ADC is a sigma-delta ADC.

7. The class-D amplifier of claim 1 , wherein the output stage comprises an open loop driver.

8. The class-D amplifier of claim 1 , further comprising:
a low pass filter coupled to an output of the output stage; and
wherein the load comprises at least one audio speaker coupled to the output of the low pass filter.

9. A method for detecting and suppressing analog error associated with an output stage of a class-D amplifier, comprising:
combining a digital input signal with a digital feedback signal to produce a first combined signal;
generating a digital pulse-width modulated (PWM) signal based on the first combined signal and providing the digital PWM signal to a feedback circuit;
generating an analog output signal for driving a load based on the digital PWM signal; and
generating the digital feedback signal using the feedback circuit by:
converting the digital PWM signal to an analog PWM signal,
combining the analog PWM signal and the analog output signal to generate a second combined signal, and
converting the second combined signal to a digital form.

10. The method of claim 9 , further comprising:
setting a reference voltage of the DAC and a reference voltage of the ADC to a same value.

11. The method of claim 9 , wherein combining the digital input signal with the digital feedback signal comprises:
subtracting the digital feedback signal from the digital input signal.

12. A class-D amplifier, comprising:
a first combiner operable to combine a digital input signal, a first feedback signal, and a second feedback signal to obtain a first combined signal;
a pulse width modulation stage operable to generate a pulse-width modulated (PWM) signal by comparing the first combined signal to a triangle waveform and to provide the PWM signal as the first feedback signal and as an input to a feedback circuit;
an output stage operable to generate an output signal for driving a load responsive to the PWM signal; and
the feedback circuit operable to receive the PWM signal and the output signal from the output stage and to generate the second feedback signal based thereon.

13. The class-D amplifier of claim 12 , wherein the PWM signal comprises a digital PWM signal, the output signal comprises an analog output signal, and the feedback circuit comprises:
a digital to analog converter (DAC) operable to convert the digital PWM signal to an analog PWM signal;
a second combiner operable to combine the analog PWM signal and the analog output signal to generate a second combined signal; and
an analog to digital converter (ADC) that is coupled to the second combiner and operable to convert the second combined signal from an analog form to a digital form to generate the second feedback signal.

14. The class-D amplifier of claim 13 , wherein the DAC comprises an inverter.

15. The class-D amplifier of claim 13 , wherein the second combiner comprises a first resistor, a second resistor, a third resistor, and an operational amplifier,
the first resistor having a first terminal coupled to the output stage and a second terminal coupled to an input of the operational amplifier,
the second resistor having a first terminal coupled to the output of the DAC and a second terminal coupled to the input of the operational amplifier, and
the third resistor having a first terminal coupled to an output of the operational amplifier and a second terminal coupled to the input of the operational amplifier.

16. The class-D amplifier of claim 13 , wherein a reference voltage of the DAC and a reference voltage of the ADC are equal.

17. The class-D amplifier of claim 13 , wherein the ADC is a sigma-delta ADC.

18. The class-D amplifier of claim 12 , wherein the output stage comprises an open loop driver.

19. The class-D amplifier of claim 12 , wherein the first feedback signal and the second feedback signal are digital signals.

20. The class-D amplifier of claim 12 , further comprising:
a low pass filter coupled to an output of the output stage; and
wherein the load comprises at least one audio speaker coupled to the output of the low pass filter.

Assignees

• Broadcom Corp

Inventors

• Wang Zhengyu
• Mehr Iuri
• Song Jungwoo
• Jiang Xicheng

Classifications

• H03F2200/351

  Pulse width modulation being used in an amplifying circuit · CPC title

• H03F3/217 Primary

  Class D power amplifiers; Switching amplifiers · CPC title

• H03F3/2175 Primary

  using analogue-digital or digital-analogue conversion (H03F3/2173 takes precedence) · CPC title