Network-on-chip for inter-die and intra-die communication in modularized integrated circuit devices

Patent metadata

Field	Value
Publication number	US-11036660-B2
Application number	US-201916368688-A
Country	US
Kind code	B2
Filing date	Mar 28, 2019
Priority date	Mar 28, 2019
Publication date	Jun 15, 2021
Grant date	Jun 15, 2021

Abstract

Systems or methods of the present disclosure may provide high-bandwidth, low-latency connectivity for inter-die and/or intra-die communication of a modularized integrated circuit system. Such an integrated circuit system may include a first die of fabric circuitry sector(s), a second die of modular periphery intellectual property (IP), a passive silicon interposer coupling the first die to the second die, and a modular interface that includes a network-on-chip (NOC). The modular interface may provide high-bandwidth, low-latency communication between the first die and the second, between the fabric circuitry sector(s), and between the first die and a third die.

First claim

What is claimed is:

1. An integrated circuit system, comprising:
a first die comprising one or more programmable fabric circuitry sectors;
a second die comprising modular periphery intellectual property (IP);
an interposer coupling the first die to the second die; and
a modular interface disposed in the interposer comprising a network-on-chip (NOC) having a plurality of routers, wherein the modular interface is configurable to:
provide communication between the first die and the second die via a first portion of the modular interface located between the first die and the second die;
provide communication between the one or more programmable fabric circuitry sectors via a second portion of the modular interface located between the one or more programmable fabric circuitry sectors; and
provide communication between the first die and a third die comprising additional one or more programmable fabric circuitry sectors via a third portion of the modular interface comprising a crossbar switch formed by one or more routers of the plurality of routers located between the first die and the third die.

2. The integrated circuit system of claim 1 , wherein the modular interface is configurable to provide a high-bandwidth, low-latency communication comprising transmitting and receiving signals at 0.25-0.5 terabytes per second per direction per link and at a speed double that of an operating frequency of the one or more programmable fabric circuitry sectors.

3. The integrated circuit system of claim 1 , wherein the modular periphery IP comprises a double data rate (DDR) tile, a low power DDR (LPDDR) tile, a high bandwidth memory (HBM) tile, embedded static random-access memory (eSRAM) tile, a Universal Interface Bus (UIB) tile, an input/output (I/O) tile, or any combination thereof, and wherein the modular periphery IP is configurable to perform a function associated with the programmable fabric circuitry sectors.

4. The integrated circuit system of claim 1 , wherein the plurality of routers is configurable to route data to portions of the first die or portions of the second die, wherein a router of the plurality of routers comprises:
a first port configurable to receive data from an adjacent router of the plurality of routers, transmit the data to another adjacent router of the plurality of routers, or a combination thereof;
a second port configurable to:
receive the data, via an associated router bridge, from:
a sector of the one or more programmable fabric circuitry sectors;
the modular IP; or
a combination thereof; and

transmit the data, via the associated router bridge, to:
another sector of the one or more programmable fabric circuitry sectors;
a fourth die comprising another modular IP; or
a combination thereof; and

crossbar circuitry configurable to route the data to the first port or the second port based on a destination of the data.

5. The integrated circuit system of claim 4 , wherein the associated router bridge comprises:
a clock-crossing buffer configurable to convert a protocol of data from a user logic data protocol to a router data protocol to facilitate appropriate data transmission by the NOC;
a data width converter configurable to convert a width of the data from a user logic compatible data width to a router compatible data width; and
a switch configurable to select a portion of the data held in a virtual channel for processing by the router.

6. The integrated circuit system of claim 1 , wherein second die comprises a fabric network-on-chip (FNOC) configurable to bridge the second die to the NOC.

7. The integrated circuit system of claim 1 , wherein the plurality of routers is configurable to route data to portions of the first die or portions of the second die, wherein a router of the plurality of routers comprises a virtual channel configurable to aggregate the data for downstream transmission based at least in part on a priority of the data.

8. The integrated circuit system of claim 1 , wherein the plurality of routers is configurable to route data to portions of the first die or portions of the second die, wherein a router of the plurality of routers comprises a clock-crossing buffer configurable to convert a protocol of the data from a router data protocol to a user logic data protocol.

9. A modularized integrated circuit comprising a plurality of dies and a network-on-chip (NOC) interface, wherein the NOC interface comprises:
a first router of a first die of the plurality of dies, wherein the first router is configurable to transmit data;
a second router of a second die of the plurality of dies, wherein the second router is configurable to receive the data transmitted by the first router;
one or more transmission modules coupled to the first router, wherein the one or more transmission modules are configurable to:
receive a respective portion of the data from the first router; and
transmit the respective portion of the data using a double data rate (DDR) technique with an interface clock operating at a faster frequency than a router clock that controls operations of the first router; and

one or more receiving modules coupled to the one or more transmission modules and to the second router, wherein the one or more receiving modules are configurable to:
receive the respective portion of the data from a transmission module of the one or more transmission modules associated with a respective receiving module of the one or more receiving modules;
demultiplex the respective portion of the data from a double data rate (DDR) to a single data rate (SDR); and
in response to demultiplexing the respective portion of the data, transmitting the respective portion of the data to the second router.

10. The modularized integrated circuit of claim 9 , wherein the first router is configurable to receive the data from the second router, and wherein the second router is configurable to transmit the data from the first router.

11. The modularized integrated circuit of claim 9 , comprising a word marker block coupled to the first router and the one or more transmission modules, wherein the word marker block is configurable to provide an indicator to respective portions of the data, wherein the indicator indicates a sequence in which the data is transmitted to the one or more receiving modules.

12. The modularized integrated circuit of claim 9 , comprising a word align block coupled to the second router and the one or more receiving modules, wherein the word align block is configurable to align respective portions of the data received from the second router.

13. The modularized integrated circuit of claim 12 , wherein the word align block is configurable to transmit respective portions of the data downstream in response to the data being aligned.

14. The modularized integrated circuit of claim 9 , wherein the one or more transmission modules comprise a validity transmitter configurable to transmit a validity signal to the one or more receiving modules in response to the transmitted data being valid.

15. The modularized integrated circuit of claim 9 , wherein demultiplexing the respective portion of the data from the double data rate (DDR) to the single data rate (SDR) comprises sampling the data at a rising edge of the interface clock and at a falling edge of the interface clock.

16. The modularized integrated circuit of claim 9 , wherein the interface clock operates at twice a faster frequency than the router clock.

17. The modularized integrated circuit of claim 9 , wherein the one or more transmission modules comprise a strobe generator that is

Assignees

• Intel Corp

Inventors

• Ooi George Chong Hean
• Tang Lai Guan
• Teh Chee Hak

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W70/611

  for connecting multiple chips together · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title

• H10W70/63

  Vias, e.g. via plugs · CPC title