Mapping multi-rate shading to monolithic programs

Patent metadata

Field	Value
Publication number	US-9905046-B2
Application number	US-201414492471-A
Country	US
Kind code	B2
Filing date	Sep 22, 2014
Priority date	Apr 3, 2014
Publication date	Feb 27, 2018
Grant date	Feb 27, 2018

Abstract

In multi-rate shading, a coarse-rate shading phase is added on top of existing pixel-rate phase to significantly improve performance with minimum impact to image quality. Two shading phases evaluated at different rates may be mapped to one monolithic program running on processor graphics single instruction multiple data (SIMD) engines. In one embodiment, multi-rate shading allows a single rendering pass to execute shading code at one or more different rates: per group of pixels, per pixel, and per sample.

First claim

What is claimed is:

1. A method comprising:
defining a coarse-to-pixel mapping for a group of pixels;
performing coarse pixel shading using interpolated attributes;
performing pixel shading in a hardware processor for said group using data from coarse pixel shading and the interpolated attributes; and
performing sample shading using data from pixel shading and the interpolated attributes.

2. The method of claim 1 including determining which pixels in the group are lit.

3. The method of claim 1 including using the same kernel for coarse and pixel shading.

4. The method of claim 3 including using a single instruction multiple data shader.

5. The method of claim 4 including using the same lanes for both coarse and pixel shading.

6. The method of claim 1 including performing pixel shading for the group after performing coarse shading for the group.

7. The method of claim 1 including using an instruction for switching program execution from coarse rate to pixel rate in the same kernel program running a single instruction multiple data machine.

8. The method of claim 1 including coarse shading a plurality of quads at a time and then pixel shading each of said quads successively.

9. A method comprising:
mapping coarse and pixel shading with phases into one monolithic single instruction multiple data program;
determining pixels locations in barycentric space; and
suppressing a group of pixels if all pixels in the group are unlit.

10. The method of claim 9 including compiling coarse-to pixel mapping, pixel lit mask, group of pixels, and barycentrics in a fixed function accelerator.

11. The method of claim 10 including implementing pixel-rate phases as a loop over pixel groups determined by the fixed function accelerator.

12. The method of claim 11 including setting an execution mask in each loop, using coarse-to-pixel mapping to swizzle interstage data between coarse-to-pixel rate phases, and using barycentrics to interpolate per-pixel attributes in each loop pass.

13. One or more non-transitory computer readable media storing instructions executed by a processor to perform a sequence comprising:
defining a coarse-to-pixel mapping for a group of pixels;
performing coarse pixel shading using interpolated attributes;
performing pixel shading in a hardware processor for said group using data from coarse pixel shading and the interpolated attributes; and
performing sample shading using data from pixel shading and the interpolated attributes.

14. The media of claim 13 , said sequence including determining which pixels in the group are lit.

15. The media of claim 13 , said sequence including using the same kernel for coarse and pixel shading.

16. The media of claim 15 , said sequence including using a single instruction multiple data shader.

17. The media of claim 16 , said sequence including using the same lanes for both coarse and pixel shading.

18. The media of claim 13 , said sequence including performing pixel shading for the group after performing coarse shading for the group.

19. The media of claim 13 , said sequence including using an instruction for switching program execution from coarse rate to pixel rate in the same kernel program running a single instruction multiple data machine.

20. The media of claim 13 , said sequence including coarse shading a plurality of quads at a time and then pixel shading each of said quads successively.

21. An apparatus comprising:
a hardware processor to define a coarse-to-pixel mapping for a group of pixels, perform coarse pixel shading using interpolated attributes, perform pixel shading in a hardware processor for said group using data from coarse pixel shading and the interpolated attributes, perform sample shading using data from pixel shading and the interpolated attributes; and
a storage coupled to said processor.

22. The apparatus of claim 21 , said processor to determine which pixels in the group are lit.

23. The apparatus of claim 21 , said processor to use the same kernel for coarse and pixel shading.

24. The apparatus of claim 23 , said processor to use a single instruction multiple data shader.

25. The apparatus of claim 24 , said processor to use the same lanes for both coarse and pixel shading.

26. The apparatus of claim 21 , said processor to perform pixel shading for the group after performing coarse shading for the group.

27. The apparatus of claim 21 , said processor to use an instruction for switching program execution from coarse rate to pixel rate in the same kernel program running a single instruction multiple data machine.

28. The apparatus of claim 21 , said processor to coarse shade a plurality of quads at a time and then pixel shading each of said quads successively.

29. The apparatus of claim 21 including a memory controller hub.

30. The apparatus of claim 21 including a wireless transceiver.

Assignees

• Intel Corp

Inventors

• Janczak Tomasz
• Surti Prasoonkumar

Classifications

• G06T15/005

  General purpose rendering architectures · CPC title

• G06T15/80 Primary

  Shading · CPC title

• G06T1/20 Primary

  Processor architectures; Processor configuration, e.g. pipelining · CPC title