Internal spacers for nanowire transistors and method of fabrication thereof

Patent metadata

Field	Value
Publication number	US-9508796-B2
Application number	US-201314916093-A
Country	US
Kind code	B2
Filing date	Oct 3, 2013
Priority date	Oct 3, 2013
Publication date	Nov 29, 2016
Grant date	Nov 29, 2016

Abstract

A nanowire transistor of the present description may be produced with internal spacers formed by using sacrificial spacers during the fabrication thereof. Once the nanowire transistor is formed, the sacrificial spacers, which are position between the transistor gate and the source and drains (respectively), may be removed. The sacrificial material between channel nanowires of the nanowire transistor may then be removed and a dielectric material may be deposited to fill the spaces between the channel nanowires. The dielectric material not between the channel nanowires may be removed to form the internal spacers. External spacers, which are position between the transistor gate and the source and drains (respectively), may then be formed adjacent the internal spacers and transistor channel nanowires.

First claim

What is claimed is:

1. A method of forming a nanowire transistor, comprising:
providing a microelectronic structure having:
a fin structure, having a plurality of channel nanowires, disposed on a substrate;
a gate structure abutting a portion of the fin structure, wherein the gate structure comprises a gate dielectric surrounds each of the plurality of the channel nanowires in the fin structure and a gate electrode abutting the gate dielectric;
a sacrificial spacer abutting one end of the gate electrode, wherein the sacrificial spacer abuts a portion of the fin structure that comprises the channel nanowires separated by sacrificial material; and
one of a source and a drain abutting one end of the fin structure and the sacrificial spacer;

removing the sacrificial spacer;
removing the sacrificial material from between the channel nanowires; and
depositing a dielectric material to form a spacer, wherein the dielectric material is disposed between the channel nanowires.

2. The method of claim 1 , wherein depositing the dielectric material to form the spacer comprises depositing a low-k dielectric material to form the spacer.

3. The method of claim 1 , wherein the sacrificial spacer comprises at least one of silicon dioxide, silicon nitride, and silicon oxy nitride.

4. The method of claim 1 , further including:
removing a portion of the spacer to define internal spacers between the channel nanowires; and
depositing another dielectric material, differing from that of the internal spacers to form an external spacer between the gate electrode and the one of a source and a drain, wherein the external spacer surrounds the internal spacers and the channel nanowires.

5. The method of claim 1 , wherein the sacrificial material comprises silicon and wherein the channel nanowires comprise silicon germanium.

6. The method of claim 1 , wherein the sacrificial material comprises silicon germanium layers and wherein the channel nanowires comprise silicon.

7. A method of forming a nanowire transistor, comprising:
providing a microelectronic structure having:
a fin structure, having a plurality of channel nanowires, disposed on a substrate;
a gate structure abutting a portion of the fin structure, wherein the gate structure comprises a gate dielectric surrounding each of the plurality of the channel nanowires in the fin structure and a gate electrode abutting the gate dielectric;
a first sacrificial spacer abutting one end of the gate electrode, the first sacrificial spacer abuts a portion of the fin structure that comprises the channel nanowires separated by sacrificial material;
a second sacrificial spacer abutting another end of the gate electrode, the second sacrificial spacer abuts another portion of the fin structure that comprises the plurality of channel nanowires separated by the sacrificial material;
a source abutting one end of the fin structure and the first sacrificial spacer; and
a drain abutting an opposing end of the fin structure and the second sacrificial spacer;

removing the first sacrificial spacer and the second sacrificial spacer;
removing the sacrificial material from between the channel nanowires; and
depositing a dielectric material to form a first spacer and a second spacer, wherein the dielectric material is disposed between the channel nanowires.

8. The method of claim 7 , wherein depositing the dielectric material to form the first spacer and the second spacer comprises depositing a low-k dielectric material to form the first spacer and the second spacer.

9. The method of claim 7 , wherein at least one of the first sacrificial spacer and the second sacrificial spacer comprises at least one of silicon dioxide, silicon nitride, and silicon oxy nitride.

10. The method of claim 7 , further including:
removing a portion of the first spacer and a portion of the second spacer define internal spacers between the channel nanowires; and
depositing a dielectric material, differing from that of the internal spacers, to form a first external spacer between the gate electrode and the source, and a second external spacer between the gate electrode, wherein the first external spacer and the second external spacer surrounding the internal spacers and the channel nanowires.

11. The method of claim 7 , wherein the sacrificial material comprises silicon and wherein the channel nanowires comprise silicon germanium.

12. The method of claim 7 , wherein the sacrificial material comprises silicon germanium layers and wherein the channel nanowires comprise silicon.

13. A method of forming a nanowire transistor, comprising:
forming a microelectronic substrate;
forming a stacked layer on the microelectronic substrate comprising at least one sacrificial material layer and at least one channel material layer;
forming at least one fin structure formed from the layered stack;
forming at least two sacrificial spacers across the fin structure;
forming a sacrificial gate material between the at least two sacrificial spacers;
removing a portion of the fin structure external to the sacrificial gate material and the sacrificial spacers to expose portions of the microelectronic substrate;
forming a source structure and a drain structure on the microelectronic substrate portions on opposing ends of the fin structure;
forming an interlayer dielectric layer over the source structure and the drain structure;
removing the sacrificial gate material from between the sacrificial spacers;
selectively removing the sacrificial material layers from between the channel material layer to form at least one channel nanowire;
forming a gate dielectric material to surround the channel nanowire between the at least two sacrificial spacers;
forming a gate electrode on the gate dielectric material;
removing the at least two sacrificial spacers;
selectively removing the sacrificial material layers between the channel nanowires; and
depositing a dielectric material to form at least one spacer, wherein the dielectric material is disposed between the channel nanowires.

14. The method of claim 13 , wherein depositing the dielectric material to form the at least one spacer comprises depositing a low-k dielectric material to form the at least one spacer.

15. The method of claim 13 , wherein at least one of the at least two sacrificial spacers comprises at least one of silicon dioxide, silicon nitride, and silicon oxy nitride.

16. The method of claim 13 , further including:
removing a portion of the at least one spacer to define internal spacers between the channel nanowires; and
depositing another dielectric material, differing from that of the internal spacers to form at least one external spacer surrounding the internal spacers and the channel nanowires.

17. The method of claim 13 , wherein forming a stacked layer on the microelectronic substrate comprising at least one sacrificial material layer and at least one channel material layer comprises forming the stacked layer on the microelectronic substrate comprising at least one silicon sacrificial layer and at least one silicon germanium channel layer.

18. The method of claim 13 , wherein forming a stacked layer on the microelectronic substrate comprising at least one sacrificial material layer and at least one channel material layer comprises forming the stacked layer on the microelectronic substrate comprising at least one silicon germanium sacrificial layer and at least one silicon channel layer.

Assignees

• Intel Corp

Inventors

• Kim Seiyon
• Simon Daniel A
• Rahhal-Orabi Nadia M
• Lim Chul-Hyun
• Kuhn Kelin J

Classifications

• H10P14/3462

  Nanowires · CPC title

• H10D30/6757 Primary

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D64/018

  Spacers formed inside holes at the prospective gate locations, e.g. holes left by removing dummy gates · CPC title

• H10D64/205

  Nanosized electrodes, e.g. nanowire electrodes · CPC title

• H10D62/119

  Nanowire, nanosheet or nanotube semiconductor bodies · CPC title