Quiesce reconfigurable data processor

Patent metadata

Field	Value
Publication number	US-11928512-B2
Application number	US-202117322697-A
Country	US
Kind code	B2
Filing date	May 17, 2021
Priority date	Jul 8, 2019
Publication date	Mar 12, 2024
Grant date	Mar 12, 2024

Abstract

A reconfigurable data processor comprises an array of configurable units configurable to allocate a plurality of sets of configurable units in the array to implement respective execution fragments of the data processing operation. Quiesce logic is coupled to configurable units in the array, configurable to respond to a quiesce control signal to quiesce the sets of configurable units in the array on quiesce boundaries of the respective execution fragments, and to forward quiesce ready signals for the respective execution fragments when the corresponding sets of processing units are ready. An array quiesce controller distributes the quiesce control signal to configurable units in the array, and receives quiesce ready signals for the respective execution fragments from the quiesce logic.

First claim

What is claimed is:

1. A computer-implemented method for operating a processing system including an array of configurable processing units, comprising:
configuring a spatially configurable array of configurable processing units for execution of a data processing operation, the data processing operation including a plurality of execution fragments, by configuring a plurality of resource groups of configurable processing units in the array to execute respective execution fragments of the plurality of execution fragments; and
during execution of the data processing operation using the spatially configurable array, responding to a control signal to quiesce the plurality of resource groups on quiesce boundaries of the respective execution fragments.

2. The method of claim 1 , including generating the control signal in response to an internal event originating in the array.

3. The method of claim 1 , including generating the control signal in response to an external event originating outside the array.

4. The method of claim 1 , wherein the control signal is asynchronous relative to the plurality of execution fragments.

5. The method of claim 1 , including configuring the quiesce boundaries using configuration data defining sets of configured states of execution in the processing units of the resource groups configured to execute the respective execution fragments.

6. A non-transitory computer readable storage medium impressed with computer program instructions, the instructions, when executed on a processor, implement a method comprising:
configuring a spatially configurable array of configurable processing units for execution of a data processing operation, the data processing operation including a plurality of execution fragments, by configuring a plurality of resource groups of configurable processing units in the array to execute respective execution fragments of the plurality of execution fragments; and
during execution of the data processing operation using the spatially configurable array, responding to a control signal to quiesce the plurality of resource groups on quiesce boundaries of the respective execution fragments.

7. The non-transitory computer readable storage medium of claim 6 , implementing the method further comprising generating the control signal in response to an internal event originating in the array.

8. The non-transitory computer readable storage medium of claim 6 , implementing the method further comprising generating the control signal in response to an external event originating outside the array.

9. The non-transitory computer readable storage medium of claim 6 , wherein the control signal is asynchronous relative to the plurality of execution fragments.

10. The non-transitory computer readable storage medium of claim 6 , implementing the method further comprising configuring the quiesce boundaries using configuration data defining sets of configured states of execution in the processing units of the resource groups configured to execute the respective execution fragments.

Assignees

• Sambanova Systems Inc

Inventors

• Prabhakar Raghu
• Shah Manish K
• Nataraja Pramod
• Jackson David Brian
• Leung Kin Hing
• Sivaramakrishnan Ram
• Jairath Sumti
• Grohoski Gregory Frederick

Classifications

• G06F9/3887 Primary

  controlled by a single instruction for multiple data lanes [SIMD] · CPC title

• G06F9/5027 Primary

  the resource being a machine, e.g. CPUs, Servers, Terminals · CPC title

• G06F15/80

  comprising an array of processing units with common control, e.g. single instruction multiple data processors (G06F15/82 takes precedence {; for correlation function computation G06F17/15}) · CPC title

• G06F2209/506

  Constraint · CPC title

• G06F9/3826 Primary

  Bypassing or forwarding of data results, e.g. locally between pipeline stages or within a pipeline stage · CPC title