Semiconductor integrated fluxgate device shielded by discrete magnetic plate

Patent metadata

Field	Value
Publication number	US-11921134-B2
Application number	US-202318295788-A
Country	US
Kind code	B2
Filing date	Apr 4, 2023
Priority date	Dec 8, 2017
Publication date	Mar 5, 2024
Grant date	Mar 5, 2024

Abstract

A current-sensing system includes a conductor for carrying a first electrical current generating a first magnetic field. A device, spaced from the conductor by a clearance, includes a semiconductor integrated circuit die in a package. The semiconductor integrated circuit die includes at least one elongated bar of a first ferromagnetic material magnetized by the first magnetic field; a sensor comprising a first coil wrapped around the at least one elongated bar to sense the bar's magnetization; and an electronic driver creating a second electrical current flowing through a second coil wrapped around the at least one elongated bar generating a second magnetic field to compensate the at least one bar's magnetization. The package has a first outer surface free of device terminals. A discrete plate of a second ferromagnetic material is positioned in the clearance and is conformal with the first outer surface of the package.

First claim

What is claimed is:

1. A system for sensing current, comprising:
a core of a first ferromagnetic material shaped as a toroid including an air gap;
a conductor configured for carrying a first electrical current, the conductor shaped as a wire traversing the toroid, a magnetic field due to the first current configured to generate a first magnetic flux in the toroid and across the air gap;
a device in the air gap spaced from the conductor by a clearance, the device including a semiconductor integrated circuit die in a package, the semiconductor integrated circuit die including a sensor including a first coil wrapped around at least one bar of a second ferromagnetic material configured to sense the magnetization of the at least one bar, the package having a first outer surface free of device terminals and an opposite second outer surface including exposed device terminals; and
a discrete plate of a third ferromagnetic material in the clearance, the discrete plate being conformal with the first outer surface of the package.

2. The system of claim 1 , wherein the discrete plate is flat and parallel to the first outer surface of the package.

3. The system of claim 2 , wherein the discrete plate of spaced from the first outer surface of the package by a clearance.

4. The system of claim 2 , wherein the discrete plate touches the first outer surface of the package.

5. The system of claim 1 , wherein the discrete plate has a shape that is one selected from circular and oval at least partially surrounding the package.

6. The system of claim 1 , wherein the device further includes an electronic driver configured to create a second electrical current flowing from the device to a second coil wrapped around the core, the second current in the second coil configured to generate a second magnetic flux in the toroid for compensating the first magnetic flux.

7. The system of claim 1 , wherein the third ferromagnetic material is a homogeneous alloy with a permeability greater than 500 and a saturation magnetic flux density between about 0.5 and 2.4 T.

8. The system of claim 7 , wherein the discrete plate has a thickness in a range of about 200 μm to 500 μm.

9. The system of claim 1 further including a marker on the second outer surface of the package, the marker being aligned with the at least one bar.

10. The system of claim 1 , wherein the second ferromagnetic material is a homogeneous alloy with a permeability greater than 500 and a saturation magnetic flux density between about 0.5 and 2.4 T.

11. The system of claim 1 , wherein the first ferromagnetic material is a homogeneous alloy with a saturation magnetization reached on application of about 2 mT.

Assignees

• Texas Instruments Inc

Inventors

• Lee Dok Won

Classifications

• H10W74/111

  the semiconductor body being completely enclosed · CPC title

• H10W70/657

  on sidewalls or bottom surfaces of the package substrates, interposers or redistribution layers · CPC title

• H10W46/607

  Located on parts of packages, e.g. on encapsulations or on package substrates · CPC title

• H10W46/301

  for alignment · CPC title

• H10W46/00 Primary

  Marks applied to devices, e.g. for alignment or identification · CPC title