Package architecture of scalable compute wall having compute bricks with vertically stacked dies
US-2024006395-A1 · Jan 4, 2024 · US
on sidewalls or bottom surfaces of the package substrates, interposers or redistribution layers
on sidewalls or bottom surfaces of the package substrates, interposers or redistribution layers · Cooperative Patent Classification (CPC)
Electric circuits, power, telecommunications, and semiconductors.
Related technology areas
Mapped technology topics for this CPC code.
| Metric | Value |
|---|---|
| CPC code | H10W70/657 |
| Official title | {on sidewalls or bottom surfaces of the package substrates, interposers or redistribution layers} |
| Display label | on sidewalls or bottom surfaces of the package substrates, interposers or redistribution layers |
| Total patents | 1,192 |
Filing trend
Year-over-year patent counts classified under this CPC code.
Filing activity over the last five years is declining.
| Year | Patents |
|---|---|
| 2015 | 73 |
| 2016 | 98 |
| 2017 | 127 |
| 2018 | 152 |
| 2019 | 122 |
| 2020 | 99 |
| 2021 | 101 |
| 2022 | 104 |
| 2023 | 121 |
| 2024 | 106 |
| 2025 | 73 |
| 2026 | 16 |
Representative patents
Representative publications under this CPC code from precomputed stats, or recent filings when stats are unavailable.
Method for packaging quad flat non-leaded package body, and package body
US-9224620-B2 · Dec 29, 2015 · US
Mounting block and a mounting assembly that incorporates the mounting block
US-2015373834-A1 · Dec 24, 2015 · US
Microelectronic packages and methods therefor
US-9218988-B2 · Dec 22, 2015 · US
Quad Flat No Lead Package And Method Of Making
US-2015364373-A1 · Dec 17, 2015 · US
Semiconductor devices and methods of manufacture thereof
US-9209140-B2 · Dec 8, 2015 · US
Process for Forming Package-on-Package Structures
US-2015348957-A1 · Dec 3, 2015 · US
Multilayer substrate
US-9204545-B2 · Dec 1, 2015 · US
Die package comprising die-to-wire connector and a wire-to-die connector configured to couple to a die package
US-9202789-B2 · Dec 1, 2015 · US
Semiconductor device
US-2015325530-A1 · Nov 12, 2015 · US
Apparatus and method for chip placement and molding
US-2015318239-A1 · Nov 5, 2015 · US
Method of fabricating a semiconductor package
US-2015303075-A1 · Oct 22, 2015 · US
High efficiency module
US-2015303136-A1 · Oct 22, 2015 · US
Emi shielded wafer level fan-out pop package
US-2015303149-A1 · Oct 22, 2015 · US
Single inline no-lead semiconductor package
US-2015303156-A1 · Oct 22, 2015 · US
Die package comprising die-to-wire connector and a wire-to-die connector configured to couple to a die package
US-2015303148-A1 · Oct 22, 2015 · US
Package, semiconductor device, and semiconductor module
US-2015279770-A1 · Oct 1, 2015 · US
Integrated Structure in Wafer Level Package
US-2015279776-A1 · Oct 1, 2015 · US
Apparatus and method for fingerprinting sensing
US-9147099-B2 · Sep 29, 2015 · US
Edge Coated Ceramic Substrates for Electronic Device Components
US-2015270227-A1 · Sep 24, 2015 · US
Frequently asked questions
Answers are generated from the same data shown on this page.
- What is CPC H10W70/657?
- CPC H10W70/657 is the Cooperative Patent Classification code for “on sidewalls or bottom surfaces of the package substrates, interposers or redistribution layers.”
- How many patents are filed under CPC H10W70/657 (on sidewalls or bottom surfaces of the package substrates, interposers or redistribution layers)?
- Our database includes 1,192 publications tagged with this CPC code.
- Is patent activity under CPC H10W70/657 growing?
- Publication counts under this code: 106 in 2024 vs 73 in 2025 (latest complete years).