Lateral recess measurement in a semiconductor specimen

US11921063B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11921063-B2
Application numberUS-202117382280-A
CountryUS
Kind codeB2
Filing dateJul 21, 2021
Priority dateJul 21, 2021
Publication dateMar 5, 2024
Grant dateMar 5, 2024

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Abstract

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There is provided a system and method of measuring a lateral recess in a semiconductor specimen, comprising: obtaining a first image acquired by collecting SEs emitted from the surface of the specimen, and a second image acquired by collecting BSEs scattered from an interior region of the specimen between the surface and a target second layer, the specimen scanned using an electron beam with a landing energy selected to penetrate to a depth corresponding to the target second layer; generating a first GL waveform based on the first image, and a second GL waveform based on the second image; estimating a first width of the first layers based on the first GL waveform, and a second width with respect to at least the target second layer based on the second GL; and measuring a lateral recess based on the first width and the second width.

First claim

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The invention claimed is: 1. A computerized system of measuring a lateral recess in a semiconductor specimen, the semiconductor specimen comprising a stack of a first type of one or more first layers and a second type of one or more second layers deposited alternately on each other, the second layers being at least partially etched, thereby forming a lateral recess between each given second layer and two first layers adjacent thereto, the system comprising: an electron beam tool configured to: scan the semiconductor specimen using an electron beam with a landing energy specifically selected to penetrate to a predefined depth corresponding to a target second layer of the specimen; and acquire a first image by collecting secondary electrons (SE) emitted from a surface of the specimen, and acquire a second image by collecting backscattered electrons (BSE) scattered from an interior region of the specimen between the surface and the target second layer, the first image informative of a surface profile of the specimen, the second image informative of an interior structure of the interior region; and a processing and memory circuitry (PMC) operatively connected to the electron beam tool and configured to: generate a first gray level (GL) waveform informative of GL intensity distribution of the first image, and a second GL waveform informative of GL intensity distribution of the second image; estimate a first width of the one or more first layers based on the first GL waveform and a second width with respect to at least the target second layer based on the second GL waveform; and measure a lateral recess with respect to the target second layer based on the first width and the second width. 2. The computerized system according to claim 1 , wherein the semiconductor specimen comprises a Gate All Around (GAA) device, and wherein the first layers are made of Silicon, and the second layers are made of silicon germanium. 3. The computerized system according to claim 1 , wherein the target second layer is a top second layer of the one or more second layers, and the measured lateral recess is a top-layer lateral recess formed between the top second layer and adjacent first layers thereof. 4. The computerized system according to claim 3 , wherein the PMC is further configured to measure an average lateral recess with respect to a subsequent second layer following the top second layer, and derive a subsequent-layer lateral recess based on the average lateral recess and the top-layer lateral recess. 5. The computerized system according to claim 1 , wherein the target second layer is a subsequent second layer following a top second layer, and the measured lateral recess is an average lateral recess of a top-layer lateral recess formed between the top second layer and adjacent first layers thereof and a subsequent lateral recess formed between the subsequent second layer and adjacent first layers thereof. 6. The computerized system according to claim 1 , wherein the SEs are collected by an array of SE detectors, and the BSEs are collected by at least one BSE detector. 7. The computerized system according to claim 1 , wherein the landing energy to penetrate to the predefined depth corresponding to the target second layer is specifically selected based on a comparison between a number of BSEs with respect to a reference specimen with no lateral recess, and a number of BSEs with respect to the semiconductor specimen. 8. The computerized system according to claim 1 , wherein the estimating the first width comprises estimating first topo-points on the first GL waveform by calculating derivatives along the first GL waveform, applying a predefined derivative threshold on the first GL waveform, giving rise to the first topo-points, and measuring the first width between the first topo-points. 9. The computerized system according to claim 1 , wherein the estimating the second width comprises estimating second topo-points on the second GL waveform by applying a predefined GL threshold on the second GL waveform, giving rise to the second topo-points, and measuring the second width between the second topo-points. 10. The computerized system according to claim 1 , wherein the PMC is further configured to calibrate the measured lateral recess with respect to reference measurement data obtained from a Transmission Electron Microscope (TEM). 11. The computerized system according to claim 10 , wherein the calibration is based on a correlation relationship previously derived between corresponding measurement data from the electron beam tool and the reference measurement data obtained from the TEM. 12. A computerized method of measuring a lateral recess in a semiconductor specimen, the semiconductor specimen comprising a stack of a first type of one or more first layers and a second type of one or more second layers deposited alternately on each other, the second layers being at least partially etched, thereby forming a lateral recess between each given second layer and two first layers adjacent thereto, the method performed by a processing and memory circuitry (PMC) and comprising: obtaining a first image acquired by collecting secondary electrons (SE) emitted from a surface of the specimen, and a second image acquired by collecting backscattered electrons (BSE) scattered from an interior region of the specimen between the surface and a target second layer, wherein the semiconductor specimen is scanned using an electron beam with a landing energy specifically selected to penetrate to a predefined depth corresponding to the target second layer, and wherein the first image is informative of a surface profile of the specimen, and the second image is informative of an interior structure of the interior region; generating a first gray level (GL) waveform informative of GL intensity distribution of the first image, and a second GL waveform informative of GL intensity distribution of the second image; estimating a first width of the first layers based on the first GL waveform and a second width with respect to at least the target second layer based on the second GL; and measuring a lateral recess with respect to the target second layer based on the first width and the second width. 13. The computerized method according to claim 12 , wherein the target second layer is a top second layer of the one or more second layers, and the measured lateral recess is a top-layer lateral recess formed between the top second layer and adjacent first layers thereof. 14. The computerized method according to claim 13 , further comprising measuring an average lateral recess with respect to a subsequent second layer following the top second layer, and deriving a subsequent-layer lateral recess based on the average lateral recess and the top-layer lateral recess. 15. The computerized method according to claim 12 , wherein the target second layer is a subsequent second layer following a top second layer, and the measured lateral recess is an average lateral recess of a top-layer lateral recess formed between the top second layer and adjacent first layers thereof and a subsequent lateral recess formed between the subsequent second layer and adjacent first layers thereof. 16. The computerized method according to claim 12 , wherein the landing energy to penetrate to the predefined depth corresponding to the target second layer, is specifically selected based on a comparison between a number of BSEs with respect to a reference specimen with no lateral recess, and a number of BSEs with respect to the semiconductor specimen. 17. The computerized method ac

Assignees

Inventors

Classifications

  • characterised by multiple measurements, corrections, marking or sorting processes · CPC title

  • H10P74/203Primary

    Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects · CPC title

  • characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

  • having gates fully surrounding the channels, e.g. gate-all-around · CPC title

  • Combination of two or more measurements, at least one measurement being that of secondary emission, e.g. combination of secondary electron [SE] measurement and back-scattered electron [BSE] measurement · CPC title

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What does patent US11921063B2 cover?
There is provided a system and method of measuring a lateral recess in a semiconductor specimen, comprising: obtaining a first image acquired by collecting SEs emitted from the surface of the specimen, and a second image acquired by collecting BSEs scattered from an interior region of the specimen between the surface and a target second layer, the specimen scanned using an electron beam with a …
Who is the assignee on this patent?
Applied Materials Israel Ltd
What technology area does this patent fall under?
Primary CPC classification H10P74/203. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Mar 05 2024 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).