Vertical semiconductor device and fabrication method thereof

Patent metadata

Field	Value
Publication number	US-11917820-B2
Application number	US-202117368630-A
Country	US
Kind code	B2
Filing date	Jul 6, 2021
Priority date	Mar 15, 2019
Publication date	Feb 27, 2024
Grant date	Feb 27, 2024

Abstract

A method for fabricating semiconductor device includes forming an alternating stack that includes a lower multi-layered stack and an upper multi-layered stack by alternately stacking a dielectric layer and a sacrificial layer over a substrate, forming a vertical trench that divides the upper multi-layered stack into dummy stacks, and forming an asymmetric stepped trench that is extended downward from the vertical trench to divide the lower multi-layered stack into a pad stack and a dummy pad stack, wherein forming the asymmetric stepped trench includes forming a first stepped sidewall that is defined at an edge of the pad stack, and forming a second stepped sidewall that is defined at an edge of the dummy pad stack and occupies less area than the first stepped sidewall.

First claim

What is claimed is:

1. A vertical semiconductor device, comprising:
a substrate;
a gate pad stack and a dummy gate pad stack that are formed over the substrate and divided by an asymmetric stepped trench;
a first dummy stack formed over the gate pad stack; and
a second dummy stack formed over the dummy gate pad stack,
wherein the first dummy stack and the second dummy stack are divided by a vertical trench, and
wherein the first and second dummy stacks are electrically isolated structures.

2. The vertical semiconductor device of claim 1 , wherein the asymmetric stepped trench includes:
a first stepped sidewall that is defined at an edge of the gate pad stack; and
a second stepped sidewall that is defined at an edge of the dummy gate pad stack facing the first stepped sidewall, and
the first stepped sidewall and the second stepped sidewall have an asymmetric structure of different occupying areas.

3. The vertical semiconductor device of claim 2 , wherein the second stepped sidewall occupies a less area than the first stepped sidewall.

4. The vertical semiconductor device of claim 2 , wherein the first stepped sidewall includes a plurality of first steps, and the second stepped sidewall includes a plurality of second steps, and
the second steps are formed to have a greater height than the first steps.

5. The vertical semiconductor device of claim 4 , wherein each of the first steps and the second steps includes a stack of a conductive layer and a dielectric layer, and
the first steps include a stack of a pair of the conductive layer and the dielectric layer, and the second steps include a stack of at least two pairs of the conductive layer and the dielectric layer.

6. The vertical semiconductor device of claim 2 , wherein the first stepped sidewall and the second stepped sidewall have the same height.

7. The vertical semiconductor device of claim 6 , wherein the first stepped sidewall includes a plurality of first steps, and the second stepped sidewall includes a plurality of second steps, and
the number of the second steps is smaller than the number of the first steps.

8. The vertical semiconductor device of claim 2 , wherein the second stepped sidewall is formed to have a steeper tilt than the first stepped sidewall.

9. The vertical semiconductor device of claim 1 , further comprising:
a gate electrode stack extended from the gate pad stack,
wherein the gate electrode stack includes:
gate electrodes and dielectric layers extended from the gate pad stack in a direction parallel to the substrate; and
a vertical pillar structure that is perpendicular to the substrate by penetrating through the gate electrodes and the dielectric layers.

10. The vertical semiconductor device of claim 1 , wherein the first and second dummy stacks each include a plurality of conductive layers alternately stacked with a plurality of dielectric layers.

11. The semiconductor device of claim 10 , wherein each of the first and second dummy stacks comprises at least four conductive layers and four dielectric layers.

Assignees

• Sk Hynix Inc

Inventors

• Kim Eun-Ho
• Jung Eun-Joo
• Yoo Jong-Hyun
• Yun Ki-Jun
• Lee Sung-Hoon

Classifications

• H10B43/20 Primary

  characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels · CPC title

• H10B43/10

  characterised by the top-view layout · CPC title

• H10B43/30

  characterised by the memory core region · CPC title

• H10B43/40

  characterised by the peripheral circuit region · CPC title

• H10B69/00 Primary

  Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices · CPC title