Semiconductor device and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-9929093-B2
Application number	US-201615131935-A
Country	US
Kind code	B2
Filing date	Apr 18, 2016
Priority date	Nov 16, 2015
Publication date	Mar 27, 2018
Grant date	Mar 27, 2018

Abstract

A semiconductor device includes a substrate including a cell area, a first contact area, and a second contact area; a lower stacked structure extending over the second contact area from the cell area; an upper stacked structure extending over the first contact area from the cell area, the upper stacked structure leaving the second contact area open; N (N is a natural number of 2 or more) first group of stepped grooves penetrating at least one portion of the upper stacked structure in the first contact area; and M (M is a natural number equal to or smaller than N) second group of stepped grooves penetrating at least one portion of the lower stacked structure in the second contact area.

First claim

What is claimed is:

1. A semiconductor device comprising:
a substrate including a cell area, a first contact area extending along a first direction from the cell area, and a second contact area extending along the first direction from the first contact area;
a lower stacked structure extending over the second contact area from the cell area, the lower stacked structure including first interlayer insulating layers and first conductive patterns, which are alternately stacked over the substrate;
an upper stacked structure extending over the first contact area from the cell area, the upper stacked structure including second interlayer insulating layers and second conductive patterns, which are alternately stacked on the lower stacked structure;
first stepped grooves each penetrating at least one portion of the upper stacked structure in the first contact area, wherein each of the first stepped grooves has stepped sidewalls symmetrically opposite to each other in the first direction; and
second stepped grooves penetrating at least one portion of the lower stacked structure in the second contact area, wherein each of the second stepped grooves has stepped sidewalls symmetrically opposite to each other in the first direction and a number of the second stepped grooves is equal to or smaller than that of the first stepped grooves.

2. The semiconductor device of claim 1 , wherein the first stepped grooves include stepped grooves formed in a same layout as the second stepped grooves.

3. The semiconductor device of claim 1 , wherein bottom surfaces of the first stepped grooves and the second stepped grooves are disposed at different heights.

4. The semiconductor device of claim 1 , further comprising slits opposite to each other along a second direction intersecting the first direction with the lower and upper stacked structures interposed therebetween.

5. The semiconductor device of claim 4 , wherein the first stepped grooves include:
at least one first-type of stepped grooves extending flat along the second direction to be isolated by the slits; and
second-type of stepped grooves disposed along the first direction while being spaced apart from each other, the second-type of stepped grooves each including a first outbox area formed deeper than the first-type of stepped grooves and a first inbox area formed deeper than the first outbox area inside the first outbox area.

6. The semiconductor device of claim 5 , wherein the first-type of stepped grooves includes:
a select step structure adjacent to the cell area; and
a word line step structure disposed between the select step structure and the second-type of stepped grooves, the word line step structure including a larger number of steps than the select step structure and formed deeper than the select step structure.

7. The semiconductor device of claim 5 , wherein the first outbox areas or the first inbox areas of the second-type of stepped grooves are arranged in a zigzag pattern along the first direction.

8. The semiconductor device of claim 7 , wherein the second interlayer insulating layers and the second conductive patterns are stacked with a height lower than the height of the upper stacked structure between the first outbox areas adjacent to each other.

9. The semiconductor device of claim 5 , wherein each of the second-type of stepped grooves includes:
a first step structure disposed in a first dummy area surrounding the first outbox area;
a second step structure formed by depressing the first step structure in the first outbox area; and
a third step structure formed by depressing the second step structure in the first inbox area.

10. The semiconductor device of claim 9 , wherein the first step structure is configured with x steps each including a pair of a second interlayer insulating layer and a second conductive pattern.

11. The semiconductor device of claim 10 , wherein a step difference between the first dummy area and the first outbox area and a step difference between the first outbox area and the first inbox area are formed by a height of one to x+1 pairs of second interlayer insulating layers and second conductive patterns.

12. The semiconductor device of claim 5 , further comprising a contact plug disposed in any one of the first inbox area and the first outbox area to be connected to any one of the second conductive patterns.

13. The semiconductor device of claim 5 , wherein the second stepped grooves include a third-type of stepped grooves disposed along the first direction while being spaced apart from each other, the third-type of stepped grooves each including a second outbox area formed deeper than the first outbox area and a second inbox area formed deeper than the second outbox area inside the second outbox area.

14. The semiconductor device of claim 13 , wherein the second stepped grooves further include a fourth-type of stepped grooves disposed between the third-type of stepped grooves and the first contact area, the fourth-type of stepped grooves formed at a position deeper than the first inbox area and higher than the second outbox area, the fourth-type of stepped grooves extending flat along the second direction to be isolated by the slits.

15. The semiconductor device of claim 13 , wherein each of the third-type of stepped grooves includes:
a fourth step structure disposed in a second dummy area surrounding the second outbox area;
a fifth step structure formed by depressing the fourth step structure in the second outbox area; and
a sixth step structure formed by depressing the fifth step structure in the second inbox area.

16. The semiconductor device of claim 15 , wherein the fourth step structure is configured with x steps each including a pair of a first interlayer insulating layer and a first conductive pattern.

17. The semiconductor device of claim 16 , wherein a step difference between the second dummy area and the second outbox area and a step difference between the second outbox area and the second inbox area are formed by a height of one to x+1 pairs of first interlayer insulating layers and first conductive patterns.

18. The semiconductor device of claim 13 , further comprising a contact plug disposed in any one of the second inbox area and the second outbox area to be connected to any one of the first conductive patterns.

19. The semiconductor device of claim 1 , further comprising a dummy step structure disposed between the first stepped grooves, the dummy step structure being configured as a portion of the upper stacked structure.

20. The semiconductor device of claim 1 , wherein the upper stacked structure is completely removed between the second stepped grooves and remains between the first stepped grooves.

Assignees

• Sk Hynix Inc

Inventors

• Lee Nam Jae

Classifications

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/435 Primary

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H01L23/5226

  Electricity · mapped topic

• H01L27/11565

  Electricity · mapped topic