Semiconductor device and semiconductor system including the same

Patent metadata

Field	Value
Publication number	US-9997257-B1
Application number	US-201715634543-A
Country	US
Kind code	B1
Filing date	Jun 27, 2017
Priority date	Dec 13, 2016
Publication date	Jun 12, 2018
Grant date	Jun 12, 2018

Abstract

A semiconductor device may include a repair address storage circuit, an address comparison circuit, and a word line selection circuit. The repair address storage circuit may store a first repair address and a second repair address. The address comparison circuit may generate a first comparison signal by comparing an input address and the first repair address, and may generate a second comparison signal by comparing the input address and the second repair address. The word line selection circuit may generate a first redundancy word line select signal corresponding to the first comparison signal and a second redundancy word line select signal corresponding to the second comparison signal, based on the first comparison signal and the second comparison signal.

First claim

What is claimed is:

1. A semiconductor device comprising:
a repair address storage circuit suitable for storing a first repair address and a second repair address;
an address comparison circuit suitable for generating a first comparison signal by comparing an input address and the first repair address, and generating a second comparison signal by comparing the input address and the second repair address; and
a word line selection circuit suitable for generating a first redundancy word line select signal corresponding to the first comparison signal and a second redundancy word line select signal corresponding to the second comparison signal, based on the first comparison signal and the second comparison signal.

2. The semiconductor device according to claim 1 , further comprising:
a nonvolatile memory circuit suitable for storing the second repair address,
wherein the repair address storage circuit receives the second repair address from the nonvolatile memory circuit and stores the second repair address in the repair address storage circuit.

3. The semiconductor device according to claim 2 , wherein the first repair address is input from an external device coupled to the semiconductor device.

4. The semiconductor device according to claim 3 , wherein the first repair address is stored in the repair address storage circuit by using a mode register command.

5. The semiconductor device according to claim 1 , wherein the address comparison circuit comprises:
a first comparator suitable for generating the first comparison signal by comparing the input address and the first repair address; and
a second comparator suitable for generating the second comparison signal by comparing the input address and the second repair address.

6. The semiconductor device according to claim 1 , wherein the word line selection circuit comprises:
a redundancy word line selection circuit suitable for generating the first redundancy word line select signal and the second redundancy word line select signal; and
a normal word line selection circuit suitable for generating a normal word line select signal based on the input address.

7. The semiconductor device according to claim 6 , wherein the redundancy word line selection circuit activates the first redundancy word line select signal in the case where the first comparison signal is activated, regardless of whether or not the second comparison signal is activated.

8. The semiconductor device according to claim 6 , wherein the redundancy word line selection circuit activates the second redundancy word line select signal in the case where the second comparison signal is activated and the first comparison signal is deactivated.

9. The semiconductor device according to claim 6 , wherein the normal word line selection circuit comprises:
a decoder enable signal generation circuit suitable for generating a decoder enable signal based on the first comparison signal and the second comparison signal; and
a decoder suitable for generating the normal word line select signal in response to the decoder enable signal.

10. The semiconductor device according to claim 9 , wherein the decoder enable signal generation circuit activates the decoder enable signal in the case where both the first comparison signal and the second comparison signal are deactivated.

11. The semiconductor device according to claim 9 , wherein the decoder activates the normal word line select signal corresponding to a value obtained by decoding the input address.

12. A semiconductor system comprising:
a semiconductor device suitable for generating a first redundancy word line select signal corresponding to a first repair address, which is provided to the semiconductor device, and a second redundancy word line select signal corresponding to a second repair address, which is recorded in the semiconductor device, based on a result of comparing an input address with each of the first repair address and the second repair address; and
a controller suitable for storing the first repair address in the semiconductor device.

13. The semiconductor system according to claim 12 , wherein the semiconductor device comprises:
a repair address storage circuit suitable for storing the first repair address and the second repair address;
an address comparison circuit suitable for generating a first comparison signal by comparing the input address and the first repair address stored in the repair address storage circuit, and generating a second comparison signal by comparing the input address and the second repair address stored in the repair address storage circuit; and
a word line selection circuit suitable for generating the first redundancy word line select signal corresponding to the first comparison signal and the second redundancy word line select signal corresponding to the second comparison signal, based on the first comparison signal and the second comparison signal.

14. The semiconductor system according to claim 13 , wherein the controller stores the first repair address in the repair address storage circuit by transmitting a mode register command to the semiconductor device.

15. The semiconductor system according to claim 13 , wherein the word line selection circuit comprises:
a redundancy word line selection circuit suitable for generating the first redundancy word line select signal and the second redundancy word line select signal; and
a normal word line selection circuit suitable for generating a normal word line select signal based on the input address.

16. The semiconductor system according to claim 15 , wherein the redundancy word line selection circuit activates the first redundancy word line select signal in the case where the first comparison signal is activated, regardless of whether or not the second comparison signal is activated.

17. The semiconductor system according to claim 15 , wherein the redundancy word line selection circuit activates the second redundancy word line select signal in the case where the second comparison signal is activated and the first comparison signal is deactivated.

18. The semiconductor system according to claim 15 , wherein the normal word line selection circuit comprises:
a decoder enable signal generation circuit suitable for generating a decoder enable signal based on the first comparison signal and the second comparison signal; and
a decoder suitable for generating the normal word line select signal in response to the decoder enable signal.

19. The semiconductor system according to claim 18 , wherein the decoder enable signal generation circuit activates the decoder enable signal in the case where both the first comparison signal and the second comparison signal are deactivated.

20. The semiconductor system according to claim 18 , wherein the decoder activates the normal word line select signal corresponding to a value obtained by decoding the input address.

Assignees

• Sk Hynix Inc

Inventors

• Lee Jung Hwan

Classifications

• G11C29/76 Primary

  using address translation or modifications · CPC title

• G11C8/12

  Group selection circuits, e.g. for memory block selection, chip selection, array selection · CPC title

• G11C8/10

  Decoders · CPC title

• G11C2029/4402

  Internal storage of test result, quality data, chip identification, repair information · CPC title

• G11C17/16

  using electrically-fusible links · CPC title