Testing a memory which includes conservative reversible logic

Patent metadata

Field	Value
Publication number	US-11435940-B2
Application number	US-202117248661-A
Country	US
Kind code	B2
Filing date	Feb 2, 2021
Priority date	Feb 2, 2021
Publication date	Sep 6, 2022
Grant date	Sep 6, 2022

Abstract

An integrated circuit device includes an array of read/write memory cells, application logic circuitry, and address decoder circuitry coupled to receive input from the application logic circuitry and to provide output to the array of memory cells. The address decoder circuitry is reversible by having a bijective transfer function from the inputs to the outputs of the address decoder circuitry, and conservative by having the same number of 1's at the input and the output. During a test, the application logic circuitry provides a test value and test ancilla bits to the address decoder circuitry. During normal operation, the application logic circuitry provides an application memory address and constant ancilla bits to the address decoder circuitry.

First claim

What is claimed is:

1. An integrated circuit device comprising:
an array of read/write memory cells;
application logic circuitry;
address decoder circuitry coupled to receive input from the application logic circuitry and to provide output to the array of memory cells, wherein:
the address decoder circuitry is reversible by having a bijective transfer function from the inputs to the outputs of the address decoder circuitry, and conservative by having the same number of l's at the input and the output;
during a test, the application logic circuitry provides a test value and test ancilla bits to the address decoder circuitry; and
during normal operation, the application logic circuitry provides an application memory address and constant ancilla bits to the address decoder circuitry.

2. The integrated circuit device of claim 1 further comprising:
a first multiplexer coupled between the application logic circuitry and the address decoder circuitry, the first multiplexer configured to provide the application memory address to the address decoder during the normal operation and to provide the test value to the address decoder circuitry during the test.

3. The integrated circuit device of claim 2 further comprising:
a second multiplexer coupled between the application logic circuitry and the address decoder circuitry, the second multiplexer configured to provide the constant ancilla bits to the address decoder circuitry during the normal operation and to provide the test ancilla bits to the address decoder circuitry during the test.

4. The integrated circuit device of claim 3 further comprising:
an XOR logic circuit coupled between the address decoder circuitry and the array of read/write memory cells, the XOR logic circuit configured to receive a decoded application memory address from the application logic circuitry as well as an output from the address decoder circuitry, and to output a decoded address that is used to access the array of read/write memory cells.

5. The integrated circuit device of claim 4 , wherein the application logic circuitry is configured to:
during a first phase of the test, set all bits in the test value to a first binary value, and set the decoded application memory address to a decoded version of a test address of the array of read/write memory cells to be used for write access during the test; and
during a second phase of the test, set all bits in the test value to a second binary value that is opposite the first binary value.

6. The integrated circuit device of claim 5 wherein application logic circuitry is further configured to:
during the second phase of the test, write data to a memory location corresponding to the decoded address output by the XOR logic circuit, wherein the write is performed using a critical timing; and
during a third phase of the test, read data from the test address of the array of read/write memory cells, wherein the read is performed using a non-critical timing.

7. The integrated circuit device of claim 4 wherein:
the application logic circuitry is configured to:
during the test, provide a test value with all bits set to one to the address decoder circuit in a first phase of the test;
during the test, provide a test value with all the bits set zero to the address decoder circuit and write a data value to a memory location corresponding to the decoded address in the array of read/write memory cells in a second phase of the test; and
prior to the second phase of the test, set the decoded application memory address to a decoded version of a test address of the array of read/write memory cells.

8. The integrated circuit device of claim 7 wherein:
the application logic circuitry is configured to, after the test:
read the data value from the test address of the array of read/write memory cells and compare the read data value to the data value written to the array of read/write memory cells during the test; and
when the read data value is not equal to the written data value, indicate a fault in the address decoder.

9. The integrated circuit device of claim 1 wherein:
the address decoder circuitry is implemented using Fredkin gates.

10. A method for testing aging effects in an integrated circuit, comprising:
during a test_mode:
setting all bits in a test value provided as input to an address decoder circuit to a first binary value;
after a predetermined time, setting all bits in the test value provided as input to the address decoder circuit to a second binary value different than the first binary value;
processing an output of the address decoder circuit and a decoded test address in a logic circuit, wherein, in the test_mode, the decoded test address is set to a decoded version of a test address in a memory device;
providing a decoded address from the logic circuit;
writing a data value at a memory location corresponding to the decoded address in the memory device; and

once the test_mode is finished,
reading contents of the memory device at the test address using a non-critical timing scheme;
comparing the data value to the contents read at the test address; and
indicating a fault when the data value does not match the contents read at the test address.

11. The method of claim 10 wherein the logic circuit is bitwise XOR logic, the method further comprising, during normal operating mode, the decoded test address is set to all zeros.

12. The method of claim 10 further comprising:
providing test ancilla bits to the address decoder circuit during the test_mode.

13. The method of claim 12 further comprising:
providing constant values for the ancilla bits to the address decoder circuit during normal operating mode.

14. The method of claim 10 wherein:
the address decoder circuit is implemented using Fredkin gates.

15. The method of claim 10 wherein:
the decoded address from the logic circuit has critical timing attributes.

16. A processing system comprising:
application logic circuitry including a processor unit configured to execute application code;
address decoder circuitry coupled to receive output from the application logic circuitry, wherein the address decoder circuit is reversible and conservative;
an exclusive OR logic circuit configured to receive an output from the address decoder circuitry and a decoded application address from the application logic circuitry;
a memory array coupled to receive a decoded address output by the exclusive OR logic circuit,
wherein, the application logic circuitry is configured to:
during a first phase of a test_mode, output a test value with all bits set to a first binary value;
during a second phase of the test_mode, output the test value with all bits of the test value set to a second binary value that is different than the first binary value, and write a data value to the memory array at a memory location corresponding to the decoded address output by the exclusive OR logic;
prior to the second phase of the test_mode, set the decoded application address to a decoded version of a test address of the memory array;
at the end of the test_mode, read contents of the memory array from the test address and compare the contents to the data value to determine whether the address decoder circuitry is operating correctly.

17. The processing system of claim 16 further comprising:
a first multiplexer coupled between the application logic circuitry and the address decoder circuitry, the first multiplexer configured to provide the application memory address to the address decoder during the normal operation and to provid

Assignees

• Nxp Bv

Inventors

• Schat Jan-Peter
• Azimane Mohamed

Classifications

• G11C2029/1802

  Address decoder · CPC title

• G11C29/18

  Address generation devices; Devices for accessing memories, e.g. details of addressing circuits · CPC title

• G11C29/16

  using microprogrammed units, e.g. state machines · CPC title

• G11C29/12 Primary

  Built-in arrangements for testing, e.g. built-in self testing [BIST] {or interconnection details} · CPC title

• G11C29/46

  Test trigger logic · CPC title