Storage device and method of data management on a storage device

US11914864B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11914864-B2
Application numberUS-202117408031-A
CountryUS
Kind codeB2
Filing dateAug 20, 2021
Priority dateJul 1, 2021
Publication dateFeb 27, 2024
Grant dateFeb 27, 2024

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A storage device includes non-volatile memory, a storage controller including a first controller processor connected to the non-volatile memory, and a second controller processor connected to the non-volatile memory, and shared memory to store a mapping table. The shared memory may be connected to the first controller processor and the second controller processor to share mapping table information between the first controller processor and the second controller processor. The storage controller may set a power mode of the first controller processor and the second controller processor based on an input/output intensity.

First claim

Opening claim text (preview).

What is claimed is: 1. A storage device comprising: non-volatile memory; a storage controller comprising: a first controller processor connected to the non-volatile memory; and a second controller processor connected to the non-volatile memory; and shared memory to store a mapping table, the shared memory being connected to the first controller processor and the second controller processor, wherein the first controller processor is configured to make a first update to the mapping table based on a first command, and the second controller processor is configured to make a second update to the mapping table based on a second command, wherein the first update includes storing a first mapping of a first logical address to a first physical address, and the second update includes storing a second mapping of a second logical address to a second physical address, wherein the storage controller is configured to change a power mode of the first controller processor from a first power mode to a second power mode based on an input/output (TO) intensity, and wherein an IO request directed for the first controller processor is transferred to the second controller processor, and data corresponding to the IO request is stored at the non -volatile memory based on information in the mapping table; wherein the storage controller is further configured to change a first number of channels associated with the first controller processor and a second number of channels associated with the second controller processor. 2. The storage device of claim 1 , wherein the non-volatile memory comprises: a first memory chip connected to a first channel; and a second memory chip connected to a second channel, and wherein the first controller processor and the second controller processor are connected to the first memory chip via the first channel and the second memory chip via the second channel. 3. The storage device of claim 2 , wherein the storage controller is further configured to adjust the first channel and the second channel controlled by the first controller processor and the second controller processor. 4. The storage device of claim 1 , wherein the IO intensity corresponds to IO per second (IOPS). 5. The storage device of claim 4 , wherein the storage controller is further configured to put the first controller processor or the second controller processor in a state in which activities are suspended to save power or a lower frequency mode in response to the IOPS being below a first threshold. 6. The storage device of claim 5 , wherein the storage controller is further configured to put a selected controller processor having a lower number of queued IO requests from among the first controller processor and the second controllerprocessor in the state in which activities are suspended to save power or the lower frequency mode in response to IOPS being below the first threshold. 7. The storage device of claim 4 , wherein the storage controller is further configured to assign a background task to the first controller processor in response to IOPS being below a first threshold. 8. The storage device of claim 7 , wherein the storage controller is further configured to reduce the first threshold in response to assigning the background task to the first controller processor. 9. The storage device of claim 1 , wherein the storage controller is configured to set the power mode of the first controller processor and the second controller processor based on IO intensity in accordance with a command received from a power manager of a host based on the IO intensity detected by a workload detector of the host. 10. A method of data management, the method comprising: receiving, at a host interface layer of a storage controller, an IO request from a host device; determining, by the storage controller, an IO intensity; determining, by the storage controller, a group of controller processors for the IO request, the group of controller processors being connected to non-volatile memory corresponding to the IO request and being connected to shared memory to share a mapping table; receiving, by a first controller processor from among the group of controller processors, a first command; making a first update, by the first controller processor, to the mapping table based on the first command, wherein the first update includes storing a first mapping of a first logical address to a first physical address; receiving, by a second controller processor from among the group of controller processors, a second command; making a second update, by the second controller processor, to the mapping table based on the second command, wherein the second update includes storing a second mapping of a second logical address to a second physical address; changing, by the storage controller from a first power mode, a first controller processor from among the group of controller processors to operate at a second power mode based on the IO intensity; and transferring the IO request from the first controller processor to a second controller processor, wherein data corresponding to the IO request is stored at the non -volatile memory based on information in the mapping table, wherein the storage controller is further configured to change a first number of channels associated with the first controller processor and a second number of channels associated with the second controller processor. 11. The method of claim 10 , wherein the first controller processor and a second controller processor of the group of controller processors are connected to a first memory chip of the non-volatile memory via a first channel and a second memory chip of the non-volatile memory via a second channel. 12. The method of claim 11 , the method further comprising: adjusting, by the storage controller, the first channel and the second channel controlled by the first controller processor and the second controller processor. 13. The method of claim 10 , wherein the IO intensity corresponds to IOPS. 14. The method of claim 13 , the method further comprising: putting, by the storage controller, the first controller processor or the second controller processor of the group of controller processors in a state in which activities are suspended to save power or a lower frequency mode in response to IOPS being below a first threshold. 15. The method of claim 14 , wherein the putting, by the storage controller, the first controller processor or the second controller processor in the state in which activities are suspended to save power or the lower frequency mode in response to TOPS being below the first threshold comprises putting a selected controller processor having a lower number of queued IO requests from among the first controller processor and the second controller processor in the state in which activities are suspended to save power or the lower frequency mode. 16. The method of claim 13 , the method further comprising: assigning, by the storage controller, a background task to the first controller processor of the group of controller processors in response to IOPS being below a first threshold. 17. The method of claim 16 , the method further comprising: reducing, by the storage controller, the first threshold in response to the assigning, by the storage controller, the background task to the first controller processor. 18. A storage device comprising: non-volatile memory; a first controller processor connected to the non-volatile memory; a second controller processor connected to the non-volatile memory; a workload detect

Assignees

Inventors

Classifications

  • G06F3/0613Primary

    in relation to throughput · CPC title

  • by changing the path, e.g. traffic rerouting, path reconfiguration · CPC title

  • Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

  • Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

  • G06F3/0683Primary

    Plurality of storage devices · CPC title

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What does patent US11914864B2 cover?
A storage device includes non-volatile memory, a storage controller including a first controller processor connected to the non-volatile memory, and a second controller processor connected to the non-volatile memory, and shared memory to store a mapping table. The shared memory may be connected to the first controller processor and the second controller processor to share mapping table informat…
Who is the assignee on this patent?
Samsung Electronics Co Ltd
What technology area does this patent fall under?
Primary CPC classification G06F3/0613. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Feb 27 2024 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 12 related publications on this page (citations in our corpus or others sharing the same primary CPC).